iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Add optional nullstr argument to log_id()	Clifford Wolf	2019-01-15	1	-1/+3
*	Fix handling of $shiftx in Verilog back-end	Clifford Wolf	2019-01-15	1	-3/+6
*	Merge pull request #788 from whitequark/master	Clifford Wolf	2019-01-15	1	-5/+17
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\| *	manual: document some gates.	whitequark	2019-01-14	1	-9/+11
\| *	manual: explain $tribuf cell.	whitequark	2019-01-14	1	-0/+10
* \|	Merge pull request #787 from whitequark/flowmap_relax	Clifford Wolf	2019-01-15	7	-35/+776
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\| *	flowmap: clean up terminology.	whitequark	2019-01-08	1	-17/+18
\| *	flowmap: implement depth relaxation.	whitequark	2019-01-08	7	-22/+762
* \|	Improve igloo2 example	Clifford Wolf	2019-01-08	4	-5/+29
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*	Fix typo in manual	Clifford Wolf	2019-01-07	1	-1/+1
*	Bugfix in $memrd sharing	Clifford Wolf	2019-01-07	1	-2/+6
*	Merge pull request #782 from whitequark/flowmap_dfs	Clifford Wolf	2019-01-07	3	-124/+243
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\| *	flowmap: construct a max-volume max-flow min-cut, not just any one.	whitequark	2019-01-06	1	-7/+10
\| *	flowmap: add -minlut option, to allow postprocessing with opt_lut.	whitequark	2019-01-04	1	-7/+21
\| *	flowmap: cleanup for clarity. NFCI.	whitequark	2019-01-04	3	-107/+179
\| *	flowmap: improve debug graph output. NFC.	whitequark	2019-01-04	1	-47/+76
\| *	flowmap: add link to longer version of paper. NFC.	whitequark	2019-01-04	1	-2/+3
* \|	Switch "bugpoint" from system() to run_command()	Clifford Wolf	2019-01-07	1	-1/+1
* \|	Merge pull request #783 from whitequark/bugpoint	Clifford Wolf	2019-01-07	2	-1/+370
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\| * \|	bugpoint: new pass.	whitequark	2019-01-07	2	-1/+370
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* \|	Merge pull request #780 from phire/rename_from_wire	Clifford Wolf	2019-01-06	1	-0/+66
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\| * \|	Rename cells based on the wires they drive.	Scott Mansell	2019-01-06	1	-0/+66
* \| \|	Add skeleton Yosys-Libero igloo2 example project	Clifford Wolf	2019-01-05	5	-0/+44
* \| \|	Bugfix in Verilog string handling	Clifford Wolf	2019-01-05	1	-1/+1
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* \|	Merge pull request #777 from mmicko/achronix_cell_sim_fix	Clifford Wolf	2019-01-04	1	-1/+1
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\| * \|	Fix cells_sim.v for Achronix FPGA	Miodrag Milanovic	2019-01-04	1	-1/+1
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* \|	Remove -m32 Verific eval lib build instructions	Clifford Wolf	2019-01-04	1	-29/+0
* \|	Merge pull request #776 from mmicko/unify_noflatten	Clifford Wolf	2019-01-04	4	-8/+16
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\| * \|	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	4	-8/+16
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* /	Update Verific default path	Clifford Wolf	2019-01-04	1	-1/+1
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*	Merge pull request #775 from whitequark/opt_flowmap	Clifford Wolf	2019-01-03	3	-1/+875
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\| *	flowmap: new techmap pass.	whitequark	2019-01-03	3	-1/+875
* \|	Merge pull request #770 from whitequark/opt_expr_cmp	Clifford Wolf	2019-01-02	3	-97/+178
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\| *	opt_expr: improve simplification of comparisons with large constants.	whitequark	2019-01-02	2	-70/+65
\| *	opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.	whitequark	2019-01-02	2	-31/+42
\| *	opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.	whitequark	2019-01-02	2	-32/+40
\| *	opt_expr: simplify any unsigned comparisons with all-0 and all-1.	whitequark	2019-01-02	3	-17/+84
* \|	Merge pull request #755 from Icenowy/anlogic-dram-init	Clifford Wolf	2019-01-02	6	-2/+96
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\| * \|	anlogic: implement DRAM initialization	Icenowy Zheng	2018-12-20	6	-2/+96
* \| \|	Merge branch 'master' of github.com:YosysHQ/yosys	Clifford Wolf	2019-01-02	11	-35/+256
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\| * \ \	Merge pull request #750 from Icenowy/anlogic-ff-init	Clifford Wolf	2019-01-02	3	-17/+45
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\| \| * \| \|	anlogic: set the init value of DFFs	Icenowy Zheng	2018-12-18	2	-14/+15
\| \| * \| \|	Add "dffinit -noreinit" parameter	Icenowy Zheng	2018-12-18	1	-1/+14
\| \| * \| \|	Add "dffinit -strinit high low"	Icenowy Zheng	2018-12-18	1	-2/+16
\| * \| \| \|	Merge pull request #773 from whitequark/opt_lut_elim_fixes	Clifford Wolf	2019-01-02	1	-8/+31
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\| \| * \| \| \|	opt_lut: reflect changes in sigmap.	whitequark	2019-01-02	1	-0/+2
\| \| * \| \| \|	opt_lut: use a worklist, and revisit cells affected by elimination.	whitequark	2019-01-02	1	-3/+10
\| \| * \| \| \|	opt_lut: count eliminated cells, and set opt.did_something for them.	whitequark	2019-01-02	1	-6/+20
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\| * \| \| \|	Merge pull request #772 from whitequark/synth_lut	Clifford Wolf	2019-01-02	2	-7/+41
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\| \| * \| \| \|	synth_ice40: use 4-LUT coarse synthesis mode.	whitequark	2019-01-02	1	-1/+1