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* | Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-211-21/+27
* | Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-211-2/+4
* | Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
* | Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-218-0/+215
* | Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-211-17/+65
* | Progress in presentationClifford Wolf2014-02-215-19/+177
* | Progress in presentationClifford Wolf2014-02-204-11/+51
* | Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-201-4/+21
* | Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-201-0/+79
* | Added "extract -map %<design_name>"Clifford Wolf2014-02-201-10/+30
* | Added "design -push" and "design -pop"Clifford Wolf2014-02-202-8/+49
* | Progress in presentationClifford Wolf2014-02-205-0/+207
* | Added connwrappers commandClifford Wolf2014-02-202-0/+206
* | Cleanups in handling of read_verilog -defer and -icellsClifford Wolf2014-02-201-6/+7
* | Progress in presentationClifford Wolf2014-02-2010-10/+152
* | Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-192-0/+170
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-182-50/+99
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| * | Added "sat -dump_cnf"Clifford Wolf2014-02-181-5/+34
| * | Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-181-31/+31
| * | Improved non-verbose ezSAT::printDIMACS() formatClifford Wolf2014-02-181-1/+6
| * | Added "sat -initsteps"Clifford Wolf2014-02-181-14/+29
* | | Progress in presentationClifford Wolf2014-02-186-3/+72
* | | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-181-0/+39
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* | Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-178-8/+31
* | Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-171-5/+9
* | Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-171-0/+114
* | Progress in presentationClifford Wolf2014-02-173-9/+37
* | Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-171-12/+12
* | Progress in presentationClifford Wolf2014-02-165-1/+80
* | Added some additional checks to techmapClifford Wolf2014-02-161-0/+14
* | Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-161-0/+23
* | Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-161-2/+2
* | Added a warning note about error reporting to read_verilog help messageClifford Wolf2014-02-161-0/+5
* | Progress in presentationClifford Wolf2014-02-165-1/+79
* | Fixed use of selection in splitnets commandClifford Wolf2014-02-161-1/+1
* | Added recursion support to techmapClifford Wolf2014-02-161-260/+262
* | Progress in presentationClifford Wolf2014-02-166-3/+74
* | Progress in presentationClifford Wolf2014-02-166-1/+114
* | Improved support for constant functionsClifford Wolf2014-02-161-1/+50
* | Now we are in Yoys 0.2.0+ developmentClifford Wolf2014-02-162-3/+9
* | Tagging Yoys 0.2.0Clifford Wolf2014-02-162-5/+88
* | Added != support for relational select patternClifford Wolf2014-02-161-1/+7
* | Added iopadmap -bitsClifford Wolf2014-02-151-14/+48
* | Added ff and latch support to read_libertyClifford Wolf2014-02-151-40/+254
* | Bugfix in expression parser of read_libertyClifford Wolf2014-02-151-2/+1
* | Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-151-1/+1
* | Correctly convert constants to RTLIL (fixed undef handling)Clifford Wolf2014-02-151-11/+1
* | Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
* | Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-151-1/+1
* | Added liberty frontendClifford Wolf2014-02-152-0/+362