aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | Fixed YosysJS.create_worker() usage of this.url_prefixClifford Wolf2015-07-101-1/+1
* | Improved liberty file test caseClifford Wolf2015-07-061-1/+2
* | Updated ABCClifford Wolf2015-07-061-1/+1
* | Do not collect disabled $memwr cellsClifford Wolf2015-07-061-15/+18
* | Improved YosysJS WebWorker APIClifford Wolf2015-07-043-10/+51
* | Bugfix in fsm_extractClifford Wolf2015-07-031-3/+16
* | Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
* | Fixed trailing whitespacesClifford Wolf2015-07-02195-729/+729
* | Added opt_const -clkinvClifford Wolf2015-07-012-6/+95
* | Added logic-loop error handling to freduceClifford Wolf2015-06-301-0/+11
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-06-303-33/+145
|\ \
| * | Added YosysJS.create_worker()Clifford Wolf2015-06-283-33/+145
* | | Bugfix in chparamClifford Wolf2015-06-301-6/+5
* | | Added design->rename(module, new_name)Clifford Wolf2015-06-303-3/+9
|/ /
* | iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-201-2/+2
* | Using static mem size of 128 MB in emcc buildClifford Wolf2015-06-201-1/+1
* | Added init support to SMV back-endClifford Wolf2015-06-191-1/+3
* | Progress in SMV back-endClifford Wolf2015-06-191-64/+115
* | Progress in SMV back-endClifford Wolf2015-06-192-14/+60
* | Progress in SMV back-endClifford Wolf2015-06-184-24/+147
* | Progress in SMV back-endClifford Wolf2015-06-171-11/+72
* | Added "rename -top new_name"Clifford Wolf2015-06-173-0/+43
* | Progress in SMV back-endClifford Wolf2015-06-171-11/+64
* | Progress in SMV back-endClifford Wolf2015-06-161-3/+46
* | Added "synth -nordff -noalumacc"Clifford Wolf2015-06-151-3/+20
* | Progress in SMV back-endClifford Wolf2015-06-151-2/+95
* | Progress in SMV back-endClifford Wolf2015-06-151-7/+85
* | Added "write_smv" skeletonClifford Wolf2015-06-153-2/+265
* | Removed debug code from write_smt2Clifford Wolf2015-06-141-2/+0
* | Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-142-151/+166
* | Added "memory -nordff"Clifford Wolf2015-06-141-2/+9
* | Added write_smt2 -memClifford Wolf2015-06-141-80/+157
* | Makefile fix for YosysJS buildClifford Wolf2015-06-111-0/+4
* | Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-116-5/+16
* | Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-112-10/+215
* | AigMaker refactoringClifford Wolf2015-06-104-78/+153
* | Added "json -aig"Clifford Wolf2015-06-103-9/+76
* | Renamed "aig" to "aigmap"Clifford Wolf2015-06-103-10/+10
* | Fixed cellaigs port extendingClifford Wolf2015-06-103-3/+11
* | Added "aig" passClifford Wolf2015-06-093-16/+291
* | synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
* | Added cellaigs APIClifford Wolf2015-06-094-2/+173
* | Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
* | Merge branch 'verilog-backend-memV2' of github.com:wluker/yosysClifford Wolf2015-06-091-54/+110
|\ \
| * | $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-082-58/+110
| * | Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-042-16/+20
* | | Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-081-0/+2
* | | Added log_dump() support for IdStringsClifford Wolf2015-06-082-0/+5
* | | Fixed handling of parameters with reversed rangeClifford Wolf2015-06-081-1/+1
|/ /
* | Added opt_share -share_allClifford Wolf2015-05-312-16/+32