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* minisat: add missing include guard for WASI.whitequark2020-06-212-0/+14
| | | | | Including signal.h used to be allowed in WASI by mistake, but it's an error since SDK 11.
* Merge pull request #2175 from Xiretza/missing-noreturnwhitequark2020-06-191-1/+1
|\ | | | | Add missing [[noreturn]] to log_file_error()
| * Add missing [[noreturn]] to log_file_error()Xiretza2020-06-191-1/+1
|/ | | | | | | | | | | | | Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not YS_NORETURN, so it got lost in #2173, resulting in warnings in frontends/ast/simplify.cc: frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^ frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^
* Merge pull request #2173 from whitequark/use-cxx11-final-overridewhitequark2020-06-19222-556/+545
|\ | | | | Use C++11 final/override/[[noreturn]]
| * Use C++11 [[noreturn]] attribute.whitequark2020-06-193-8/+5
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| * Use C++11 final/override keywords.whitequark2020-06-18220-548/+540
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* | Merge pull request #2174 from whitequark/fix-github-linguistwhitequark2020-06-191-0/+1
|\ \ | | | | | | Fix GitHub misidentifying *.v files as Coq
| * | Fix GitHub misidentifying *.v files as Coq.whitequark2020-06-191-0/+1
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* | Merge pull request #2171 from whitequark/cxxrtl-accessorswhitequark2020-06-191-6/+47
|\ \ | | | | | | cxxrtl: add .get() and .set() accessors on value<> and wire<>
| * | cxxrtl: add .get() and .set() accessors on value<> and wire<>.whitequark2020-06-191-6/+47
| |/ | | | | | | | | | | | | | | | | | | | | | | | | For several reasons: * They're more convenient than accessing .data. * They accommodate variably-sized types like size_t transparently. * They statically ensure that no out of range conversions happen. For now these are only provided for unsigned integers, but eventually they should be provided for signed integers too. (Annoyingly this affects conversions to/from `char` at the moment.) Fixes #2127.
* | Merge pull request #2170 from boqwxp/cutpoint-efficiencywhitequark2020-06-191-9/+10
|\ \ | |/ |/| cutpoint: Improve efficiency by iterating over module ports instead of module wires
| * cutpoint: Improve efficiency by iterating over module ports instead of ↵Alberto Gonzalez2020-06-181-9/+10
|/ | | | module wires.
* Merge pull request #2153 from boqwxp/splitnets-cleanupN. Engelhardt2020-06-181-16/+19
|\ | | | | splitnets: Cleanup and efficiency improvements
| * splitnets: Clean up pseudo-private member usageAlberto Gonzalez2020-06-131-7/+6
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| * splitnets: Slightly improve efficiency by avoiding some unnecessary lookupsAlberto Gonzalez2020-06-131-9/+13
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* | Merge pull request #2167 from whitequark/cxxrtl-fix-ndebugwhitequark2020-06-181-1/+2
|\ \ | | | | | | cxxrtl: don't compute vital values in log_assert()
| * | cxxrtl: don't compute vital values in log_assert().whitequark2020-06-171-1/+2
| | | | | | | | | | | | | | | | | | This breaks NDEBUG builds. Fixes #2166.
* | | Merge pull request #2142 from whitequark/splitnets-hdlnamewhitequark2020-06-181-0/+4
|\ \ \ | | |/ | |/| splitnets: propagate (*hdlname*) and disambiguate via start_offset
| * | splitnets: propagate (*hdlname*) and disambiguate via start_offset.whitequark2020-06-101-0/+4
| | | | | | | | | | | | This allows reliably coalescing the split wires later.
* | | Merge pull request #2164 from madebr/msvcMiodrag Milanović2020-06-184-11/+11
|\ \ \ | | | | | | | | Get yosys building on Visual Studio
| * | | msvc does not support designated initializers in structsAnonymous Maarten2020-06-171-5/+5
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| * | | MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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| * | | MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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| * | | MSVC defines TRANSPARENT tooAnonymous Maarten2020-06-171-4/+4
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* | | Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfowhitequark2020-06-171-13/+17
|\ \ \ | | | | | | | | cxxrtl: restrict the debug info of a blackbox to its ports.
| * | | cxxrtl: restrict the debug info of a blackbox to its ports.Jean-François Nguyen2020-06-161-13/+17
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* | | Merge pull request #2160 from whitequark/cxxrtl-fix-warningwhitequark2020-06-171-21/+23
|\ \ \ | | | | | | | | cxxrtl: avoid unused variable warning for transparent $memrd ports
| * | | cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.whitequark2020-06-151-21/+23
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* | | | Merge pull request #2156 from XarkLabs/masterN. Engelhardt2020-06-161-7/+7
|\ \ \ \ | |_|/ / |/| | | Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
| * | | Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* | | | Merge pull request #2159 from MerryMage/cxxrtl-mulwhitequark2020-06-151-17/+22
|\ \ \ \ | |_|/ / |/| | | cxxrtl: Implement chunk-wise multiplication
| * | | cxxrtl: Implement chunk-wise multiplicationMerryMage2020-06-151-17/+22
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* | | Merge pull request #2158 from miek/sshr-sign-extensionwhitequark2020-06-151-2/+4
|\ \ \ | |/ / |/| | cxxrtl: fix sshr sign-extension.
| * | cxxrtl: fix sshr sign-extension.Mike Walters2020-06-151-2/+4
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* | | Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11whitequark2020-06-131-1/+3
|\ \ \ | | | | | | | | kernel: guard include of signal.h more precisely
| * | | kernel: guard include of signal.h more precisely.whitequark2020-06-131-1/+3
|/ / / | | | | | | | | | | | | | | | Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM does not have signals. (Arguably Yosys was broken even before, it was just broken silently.)
* | | Merge pull request #2151 from whitequark/cxxrtl-fix-rzextwhitequark2020-06-131-2/+2
|\ \ \ | |/ / |/| | cxxrtl: fix rzext()
| * | cxxrtl: fix rzext().whitequark2020-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster.
* | | Merge pull request #2145 from whitequark/cxxrtl-splitnetswhitequark2020-06-135-67/+156
|\ \ \ | | | | | | | | cxxrtl: handle multipart signals
| * | | cxxrtl: handle multipart signals.whitequark2020-06-115-27/+94
| | | | | | | | | | | | | | | | This avoids losing design visibility when using the `splitnets` pass.
| * | | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-113-40/+62
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* | | Merge pull request #2152 from whitequark/cxxrtl-always-inlinewhitequark2020-06-131-4/+108
|\ \ \ | |_|/ |/| | cxxrtl: always inline internal cells and slice/concat operations
| * | cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
|/ / | | | | | | | | | | This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* | Merge pull request #2150 from whitequark/cxxrtl-elide-pmuxwhitequark2020-06-121-30/+16
|\ \ | | | | | | cxxrtl: elide $pmux cells
| * | cxxrtl: elide $pmux cells.whitequark2020-06-121-30/+16
|/ / | | | | | | | | On Minerva, this improves runtime by around 10%, mostly by ensuring that the logic driving FFs is packed into edge conditionals.
* | Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputswhitequark2020-06-121-20/+24
|\ \ | | | | | | cxxrtl: unbuffer output wires of toplevel module
| * | cxxrtl: annotate port direction as comments.whitequark2020-06-121-1/+8
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| * | cxxrtl: unbuffer output wires of toplevel module.whitequark2020-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason.
| * | cxxrtl: simplify unbuffering of input wires.whitequark2020-06-121-20/+17
| |/ | | | | | | This also fixes an edge case with (*keep*) input ports.
* / intel_alm: fix DFFE matchingDan Ravensloft2020-06-113-5/+5
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