| Commit message (Collapse) | Author | Age | Files | Lines |
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`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
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Remove redundant sigmaps.
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Flattening does not benefit from topologically sorting cells within
a module when processing them.
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Flatten is non-recursive and doesn't need to keep track of handled
cells.
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Flattening always does "non-recursive" mapping.
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The `celltypeMap` always maps `x` to `{x}`.
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The `design` and `map` designs are always the same when flattening.
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After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
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Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
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Support packed arrays in struct/union.
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fsm_extract: avoid calling log_signal to determine wire name
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log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
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cxxrtl: add a VCD writer using debug information
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To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
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This C API is fully featured.
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On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
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cxxrtl: add debug information to the C++ API, and add introspection via a new C API
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Compared to the C++ API, the C API currently has two limitations:
1. Memories cannot be updated in a race-free way.
2. Black boxes cannot be implemented in C.
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Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.
The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
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MacOS has even stricter stack limits in catalina.
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Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
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cxxrtl: fix implementation of $sshr cell
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Fixes #2111.
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btor backend: make not printing internal names default
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Implementation of SV structs.
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Use in-tree include directory in manual build
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This is basically the same issue as in tests/various/plugin.sh,
which uses yosys-config to compile a plugin. `yosys-config --cxxflags`
points to `$PREFIX/share/` (/usr/local/share by default), which might
not exist yet or might be out of date. Building directly from the
headers in ./share/ avoids this.
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abc9: -dff improvements
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