iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix history namespace collision	Clifford Wolf	2017-06-20	1	-10/+10
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*	Store command history when terminating with an error	Clifford Wolf	2017-06-20	3	-17/+31
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*	Switched abc "clock domain not found" error to log_cmd_error()	Clifford Wolf	2017-06-20	1	-24/+28
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*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵	Clifford Wolf	2017-06-07	5	-4/+61
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*	Fix handling of Verilog ~& and ~\| operators	Clifford Wolf	2017-06-01	1	-0/+8
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*	Update ABC to hg rev efbf7f13ea9e	Clifford Wolf	2017-05-31	1	-1/+1
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*	Add dff2ff.v techmap file	Clifford Wolf	2017-05-31	2	-0/+15
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*	Fix AIGER back-end for multiple symbols per input/latch/output/property	Clifford Wolf	2017-05-30	1	-8/+20
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*	Add "setundef -anyseq"	Clifford Wolf	2017-05-28	3	-15/+56
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*	Improve write_aiger handling of unconnected nets and constants	Clifford Wolf	2017-05-28	2	-8/+62
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*	Change default smt2 solver to yices (Yices 2 has switched its license to GPL)	Clifford Wolf	2017-05-27	1	-4/+4
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*	Add aliases for common sets of gate types to "abc -g"	Clifford Wolf	2017-05-24	1	-2/+74
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*	Add examples/osu035	Clifford Wolf	2017-05-23	4	-0/+30
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-05-23	1	-17/+70
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\| *	Merge pull request #346 from azonenberg/master	Clifford Wolf	2017-05-23	1	-17/+70
\| \|\ \| \| \| \| \| \|	greenpak4_counters: Added support for parallel output from GP_COUNTx cells
\| \| *	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	Andrew Zonenberg	2017-05-22	1	-17/+70
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* /	Add workaround for CBMC bug to SimpleC back-end	Clifford Wolf	2017-05-17	1	-1/+3
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*	Enable readline and tcl in mxe builds	Clifford Wolf	2017-05-17	3	-4/+44
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*	Add missing AndnotGate() and OrnotGate() declarations to rtlil.h	Clifford Wolf	2017-05-17	1	-13/+15
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*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	14	-91/+211
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*	Add <modname>_init() function generator to simpleC back-end	Clifford Wolf	2017-05-16	2	-88/+152
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*	Improve simplec back-end	Clifford Wolf	2017-05-16	1	-1/+1
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*	Improve simplec back-end	Clifford Wolf	2017-05-15	1	-42/+44
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*	Improve simplec back-end	Clifford Wolf	2017-05-14	3	-3/+49
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*	Improve simplec back-end	Clifford Wolf	2017-05-13	1	-25/+60
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*	Improve simplec back-end	Clifford Wolf	2017-05-12	3	-12/+78
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*	Added support for more gate types to simplec back-end	Clifford Wolf	2017-05-12	1	-1/+88
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*	Add first draft of simple C back-end	Clifford Wolf	2017-05-12	6	-0/+623
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*	Update ABC to hg rev e79576e10d72	Clifford Wolf	2017-05-11	1	-1/+1
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*	Fix boolector support in yosys-smtbmc	Clifford Wolf	2017-05-08	1	-18/+18
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*	Add support for localparam in module header	Clifford Wolf	2017-04-30	1	-1/+7
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*	Fix equiv_simple, old behavior now available with "equiv_simple -short"	Clifford Wolf	2017-04-28	1	-10/+41
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*	Add support for `resetall compiler directive	Clifford Wolf	2017-04-26	1	-0/+7
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*	Replace CRLF line endings with LF in de2i.qsf (quartus example)	Clifford Wolf	2017-04-12	1	-1098/+1098
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*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	19	-165/+165
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*	Add MAX10 and Cyclone IV items to CHANGELOG	Clifford Wolf	2017-04-07	1	-0/+13
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*	Merge pull request #337 from dh73/master	Clifford Wolf	2017-04-07	25	-0/+2255
\|\ \| \| \| \|	Add initial support for both MAX10 and Cyclone IV (E\|GX) FPGAs
\| *	Add initial support for both MAX10 and Cyclone IV (E\|GX) FPGAs	dh73	2017-04-05	25	-0/+2255
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*	Add ConstEval defaultval feature	Clifford Wolf	2017-04-05	1	-1/+8
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*	Fix gcc compiler warning	Clifford Wolf	2017-04-05	1	-1/+1
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*	Add front-end detection for *.tcl files	Clifford Wolf	2017-03-28	1	-1/+6
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*	Add minisat 00_PATCH_typofixes.patch	Clifford Wolf	2017-03-27	2	-0/+21
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*	Remove use of <fpu_control.h> in minisat	Clifford Wolf	2017-03-27	4	-18/+44
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*	Add "write_smt2 -stdt" mode	Clifford Wolf	2017-03-20	2	-37/+84
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*	Add generation of logic cells to EDIF back-end runtest.py	Clifford Wolf	2017-03-19	1	-2/+6
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*	Fix EDIF: portRef member 0 is always the MSB bit	Clifford Wolf	2017-03-19	2	-13/+14
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*	Add simple EDIF test case generator and checker	Clifford Wolf	2017-03-18	1	-0/+113
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*	Fix verilog pre-processor for multi-level relative includes	Clifford Wolf	2017-03-14	1	-4/+26
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*	Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg	Clifford Wolf	2017-03-04	2	-33/+87
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*	Add write_aiger $anyseq support	Clifford Wolf	2017-03-02	1	-0/+7
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