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* Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
|\ | | | | write_verilog: correctly emit asynchronous transparent ports
| * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
|\ \ | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state
| * | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
|\ | | | | Fixed Anlogic simulation model
| * Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ \ | | | | | | write_verilog: write $tribuf cell as ternary
| * | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | | Merge branch 'whitequark-write_verilog_keyword'Clifford Wolf2019-01-275-69/+27
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| * | Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* | Merge pull request #796 from whitequark/proc_clean_typoDavid Shah2019-01-251-1/+1
|\ \ | |/ |/| proc_clean: fix critical typo
| * proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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* Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
|\ | | | | proc_clean: fix fully def check to consider compare/signal length
| * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
|/ | | | Fixes #790.
* Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
|\ | | | | Document $tribuf and some gates
| * manual: document some gates.whitequark2019-01-141-9/+11
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| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
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* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
|\ \ | |/ |/| flowmap: implement depth relaxation
| * flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | | | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
| * flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
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* | Improve igloo2 exampleClifford Wolf2019-01-084-5/+29
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typo in manualClifford Wolf2019-01-071-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in $memrd sharingClifford Wolf2019-01-071-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #782 from whitequark/flowmap_dfsClifford Wolf2019-01-073-124/+243
|\ | | | | flowmap: construct a max-volume max-flow min-cut, not just any one
| * flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
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| * flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
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| * flowmap: cleanup for clarity. NFCI.whitequark2019-01-043-107/+179
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| * flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
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| * flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
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* | Switch "bugpoint" from system() to run_command()Clifford Wolf2019-01-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #783 from whitequark/bugpointClifford Wolf2019-01-072-1/+370
|\ \ | | | | | | bugpoint: new pass
| * | bugpoint: new pass.whitequark2019-01-072-1/+370
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical use of `bugpoint` would involve a script with a pass under test, e.g.: flowmap -relax -optarea 100 and would be invoked as: bugpoint -yosys ./yosys -script flowmap.ys -clean -cells This replaces the current design with the minimal design that still crashes the `flowmap.ys` script. `bugpoint` can also be used to perform generic design minimization using `select`, e.g. the following script: select i:* %x t:$_MUX_ %i -assert-max 0 would remove all parts of the design except for an unbroken path from an input to an output port that goes through exactly one $_MUX_ cell. (The condition is inverted.)
* | Merge pull request #780 from phire/rename_from_wireClifford Wolf2019-01-061-0/+66
|\ \ | | | | | | Rename cells based on the wires they drive.
| * | Rename cells based on the wires they drive.Scott Mansell2019-01-061-0/+66
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* | | Add skeleton Yosys-Libero igloo2 example projectClifford Wolf2019-01-055-0/+44
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ \ | | | | | | Fix cells_sim.v for Achronix FPGA
| * | Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* | Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #776 from mmicko/unify_noflattenClifford Wolf2019-01-044-8/+16
|\ \ | | | | | | Unify usage of noflatten among architectures
| * | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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