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* Add PSL parser mode to verific front-endClifford Wolf2017-02-081-2/+17
* Add "read_blif -wideports"Clifford Wolf2017-02-062-5/+77
* Fix undef propagation bug in $pmux SAT modelClifford Wolf2017-02-051-14/+4
* Update ABC to hg rev a2fcd1cc61a6Clifford Wolf2017-02-051-1/+1
* Merge pull request #304 from esden/gsed-darwinClifford Wolf2017-02-051-1/+1
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| * Use -E sed parameter instead of -r.Piotr Esden-Tempski2017-02-041-1/+1
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* Add assert check in "yosys-smtbmc -c"Clifford Wolf2017-02-041-7/+28
* Improve yosys-smtbmc cover() supportClifford Wolf2017-02-041-5/+19
* Partially implement cover() support in yosys-smtbmcClifford Wolf2017-02-043-4/+97
* Further improve cover() supportClifford Wolf2017-02-043-8/+16
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-0414-9/+38
* Add assert/assume support to verific front-endClifford Wolf2017-02-042-625/+687
* Update ABC to hg rev fe96921e5d50Clifford Wolf2017-02-011-1/+1
* Update ABC scripts to use "&nf" instead of "map"Clifford Wolf2017-02-011-3/+3
* Merge branch 'C-Elegans-opt_compare_pr'Clifford Wolf2017-01-311-0/+120
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| * Fix indenting and log messages in code merged from opt_compare_prClifford Wolf2017-01-311-102/+120
| * Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-El...Clifford Wolf2017-01-311-1/+103
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| * Refactor and generalize the comparision optimizationC-Elegans2017-01-301-22/+42
| * Do not use b.as_int() in calculation of bit setC-Elegans2017-01-211-8/+29
| * Optimize compares to powers of 2C-Elegans2017-01-164-81/+61
| * Fix issue #269, optimize signed compare with 0C-Elegans2017-01-153-0/+81
* | Improve opt_rmdff support for $dlatch cellsClifford Wolf2017-01-311-4/+22
* | Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" supportClifford Wolf2017-01-301-5/+14
* | Add $ff and $_FF_ support to equiv_simpleClifford Wolf2017-01-301-2/+2
* | Add "yosys-smtbmc --aig-noheader" and AIGER mem init supportClifford Wolf2017-01-282-8/+55
* | Be more conservative with merging large cells into FSMsClifford Wolf2017-01-261-3/+17
* | Add warnings for quickly growing FSM table size in fsm_expandClifford Wolf2017-01-261-0/+10
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-01-262-4/+1
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| * | Fix RTLIL::Memory::start_offset initializationClifford Wolf2017-01-251-0/+1
| * | Merge pull request #293 from thoughtpolice/minor-cleanupClifford Wolf2017-01-161-4/+0
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| | * | passes/hierarchy: delete some dead codeAustin Seipp2017-01-151-4/+0
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* / / Add "enum" and "typedef" lexer supportClifford Wolf2017-01-172-1/+4
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* / Fix bug in AstNode::mem2reg_as_needed_pass2()Clifford Wolf2017-01-151-0/+2
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* Fix $initstate handling bug in yosys-smtbmcClifford Wolf2017-01-111-0/+2
* Update ABC to hg id f8cadfe3861fClifford Wolf2017-01-111-3/+3
* Updated ABC to hg id 38b26a543f1dClifford Wolf2017-01-081-1/+1
* Fixed handling of local memories in functionsClifford Wolf2017-01-051-2/+2
* Added "check -initdrv"Clifford Wolf2017-01-041-3/+82
* Added handling of local memories and error for local decls in unnamed blocksClifford Wolf2017-01-041-1/+10
* Implicitly set "yosys-smtbmc --noprogress" on windowsClifford Wolf2017-01-041-3/+4
* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
* Fixed "yosys-smtbmc --noprogress"Clifford Wolf2017-01-041-1/+1
* Added Verilog $rtoi and $itor supportClifford Wolf2017-01-031-24/+30
* Handle "always 1" like "always -1" in .smtc filesClifford Wolf2017-01-021-7/+5
* Added cell port resizing to hierarchy passClifford Wolf2017-01-011-0/+56
* Updated ABC to hg id 55cd83f432c0Clifford Wolf2016-12-311-1/+1
* Bugfix in RTLIL::SigSpec::remove2()Clifford Wolf2016-12-311-3/+4
* Updated ABC to hg id 8c6a635f7a20Clifford Wolf2016-12-291-1/+1
* Improved write_json help messageClifford Wolf2016-12-291-0/+4
* Updated ABC to hg id f591c081d5e7Clifford Wolf2016-12-261-1/+1
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