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| | * | | | Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
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| | * | | | Fix typo and commentsEddie Hung2019-07-091-4/+4
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| | * | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-0916-79/+348
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| | * | | | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
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| | * | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
| | * | | | Fix spacingEddie Hung2019-07-091-1/+1
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| | * | | | Fix spacingEddie Hung2019-07-091-1/+1
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| | * | | | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
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| | * | | | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
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| | * | | | Add one more commentEddie Hung2019-07-081-0/+3
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| | * | | | Less thinkingEddie Hung2019-07-081-3/+3
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| | * | | | RewordEddie Hung2019-07-081-2/+2
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| | * | | | synth_xilinx to call "synth -run coarse" with "-keepdc"Eddie Hung2019-07-081-2/+2
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| | * | | | Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7muxEddie Hung2019-07-084-8/+25
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| | * | | | | Map $__XILINX_SHIFTX in a more balanced mannerEddie Hung2019-07-081-36/+49
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| | * | | | | CapitalisationEddie Hung2019-07-081-1/+1
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| | * | | | | Add synth_xilinx -widemux recommended valueEddie Hung2019-07-081-1/+1
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| | * | | | | Fixes for 2:1 muxesEddie Hung2019-07-082-5/+30
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| | * | | | | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
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| | * | | | | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
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| | * | | | | Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7muxEddie Hung2019-07-081-5/+11
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| | * | | | | | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
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| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-088-90/+60
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| * | \ \ \ \ \ \ Merge pull request #1177 from YosysHQ/clifford/asyncClifford Wolf2019-07-105-8/+135
| |\ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|/ | |/| | | | | | | Fix clk2fflogic adff reset semantic to negative hold time on reset
| | * | | | | | | Fix tests/various/async FFL testClifford Wolf2019-07-092-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Improve tests/various/async, disable failing ffl testClifford Wolf2019-07-092-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Add tests/various/async.{sh,v}Clifford Wolf2019-07-092-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Improve tests/various/run-test.shClifford Wolf2019-07-091-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Add tests/simple_abc9/.gitignoreClifford Wolf2019-07-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | synth_ecp5: Fix typo in copyright headerDavid Shah2019-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | Merge pull request #1174 from YosysHQ/eddie/fix1173Clifford Wolf2019-07-091-0/+3
| |\ \ \ \ \ \ \ \ | | | |_|_|_|_|_|/ | | |/| | | | | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
| | * | | | | | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zeroEddie Hung2019-07-091-0/+3
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| * | | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | write_verilog: fix placement of case attributes
| | * | | | | | | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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| * | | | | | | Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdcEddie Hung2019-07-093-15/+3
| |\ \ \ \ \ \ \ | | |_|/ / / / / | |/| | | | | | Revert "Add "synth -keepdc" option"
| | * | | | | | Revert "Add "synth -keepdc" option"Eddie Hung2019-07-093-15/+3
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| * | | | | | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | | | Rename __builtin_bswap32 -> bswap32
| | * | | | | Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
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| * | | | | | Merge pull request #1168 from whitequark/bugpoint-processesClifford Wolf2019-07-092-17/+105
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | Add support for processes in bugpoint
| | * | | | | | bugpoint: add -assigns and -updates options.whitequark2019-07-091-9/+81
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| | * | | | | | proc_clean: add -quiet option.whitequark2019-07-091-8/+24
| | | |_|/ / / | | |/| | | | | | | | | | | | | | | | | | This is useful for other passes that call it often, like bugpoint.
| * | | | | | Merge pull request #1169 from whitequark/more-proc-cleanupsClifford Wolf2019-07-095-22/+168
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | A new proc_prune pass
| | * | | | | | proc_prune: promote assigns to module connections when legal.whitequark2019-07-093-33/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.)
| | * | | | | | proc_prune: new pass.whitequark2019-07-093-1/+138
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The proc_prune pass is similar in nature to proc_rmdead pass: while proc_rmdead removes branches that never become active because another branch preempts it, proc_prune removes assignments that never become active because another assignment preempts them. Genrtlil contains logic similar to the proc_prune pass, but their purpose is different: genrtlil has to prune assignments to adapt the semantics of blocking assignments in HDLs (latest assignment wins) to semantics of assignments in RTLIL processes (assignment in the most specific case wins). On the other hand proc_prune is a general purpose RTLIL simplification that benefits all frontends, even those not using the Yosys AST library. The proc_prune pass is added to the proc script after proc_rmdead, since it gives better results with fewer branches.
| * | | | | | Merge pull request #1163 from whitequark/more-case-attrsClifford Wolf2019-07-093-16/+28
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | More support for case rule attributes
| | * | | | | | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This appears to be an omission.
| | * | | | | | proc_mux: consider \src attribute on CaseRule.whitequark2019-07-081-10/+16
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| | * | | | | | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attributes are not permitted in that position by Verilog grammar.
| | * | | | | | genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
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| * | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrsClifford Wolf2019-07-093-5/+15
| |\| | | | | | | | | | | | | | | | | | | | | | Allow attributes on individual switch cases in RTLIL
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