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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
3
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+1
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Move clkpart into passes/hierarchy
Eddie Hung
2019-11-22
3
-1
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+1
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-51
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+39
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Remove redundant flatten
Eddie Hung
2019-11-22
1
-2
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+0
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submod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung
2019-11-22
1
-48
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+39
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Stray dump
Eddie Hung
2019-11-22
1
-1
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+0
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-2
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+38
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Constant driven signals are also an input to submodules
Eddie Hung
2019-11-22
1
-2
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+10
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Add another test with constant driver
Eddie Hung
2019-11-22
1
-0
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+28
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-1
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+0
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Oops
Eddie Hung
2019-11-22
1
-1
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+0
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
1
-8
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+9
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Only action if there is more than one clock domain
Eddie Hung
2019-11-22
1
-7
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+8
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Replace TODO
Eddie Hung
2019-11-22
1
-1
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+1
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Add testcase for signal used as part input part output
Eddie Hung
2019-11-22
1
-0
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+5
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write_xaiger back to working with whole modules only
Eddie Hung
2019-11-22
1
-5
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+2
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-1
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+44
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Cleanup spacing
Eddie Hung
2019-11-22
1
-2
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+1
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sigmap(wire) should inherit port_output status of POs
Eddie Hung
2019-11-22
1
-1
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+19
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Add testcase
Eddie Hung
2019-11-22
1
-0
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+26
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
2
-1
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+2
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Brackets
Eddie Hung
2019-11-22
1
-1
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+1
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Entry in Makefile.inc
Eddie Hung
2019-11-22
1
-0
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+1
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
15
-23
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+591
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Add to CHANGELOG
Eddie Hung
2019-11-22
1
-0
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+1
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New 'clkpart' to {,un}partition design according to clock/enable
Eddie Hung
2019-11-22
1
-0
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+268
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Merge pull request #1517 from YosysHQ/clifford/optmem
Clifford Wolf
2019-11-22
3
-0
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+146
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Add "opt_mem" pass
Clifford Wolf
2019-11-22
3
-0
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+146
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Merge pull request #1515 from YosysHQ/clifford/svastuff
Clifford Wolf
2019-11-22
2
-7
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+39
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Add Verific support for SVA nexttime properties
Clifford Wolf
2019-11-22
1
-0
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+22
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Improve handling of verific primitives in "verific -import -V" mode
Clifford Wolf
2019-11-22
1
-2
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+2
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Add Verific SVA support for "always" properties
Clifford Wolf
2019-11-22
1
-5
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+15
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Merge pull request #1511 from YosysHQ/dave/always
Clifford Wolf
2019-11-22
6
-9
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+126
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Update CHANGELOG and README
David Shah
2019-11-22
2
-0
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+7
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sv: Add tests for SV always types
David Shah
2019-11-21
1
-0
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+63
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proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
David Shah
2019-11-21
1
-4
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+16
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sv: Correct parsing of always_comb, always_ff and always_latch
David Shah
2019-11-21
2
-5
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+40
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gowin: Remove show command from tests.
Marcin Kościelnicki
2019-11-22
1
-1
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+0
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gowin: Add missing .gitignore entries
Marcin Kościelnicki
2019-11-22
1
-0
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+2
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Merge pull request #1507 from YosysHQ/clifford/verificfixes
Clifford Wolf
2019-11-20
2
-6
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+9
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Correctly treat empty modules as blackboxes in Verific
Clifford Wolf
2019-11-20
1
-1
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+1
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Do not rename VHDL entities to "entity(impl)" when they are top modules
Clifford Wolf
2019-11-20
2
-5
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+8
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Revert "write_xaiger to not use module POs but only write outputs if driven"
Eddie Hung
2019-11-22
1
-23
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+11
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Missing endmodule
Eddie Hung
2019-11-22
1
-0
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+1
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write_xaiger to not use module POs but only write outputs if driven
Eddie Hung
2019-11-21
1
-11
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+23
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When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
Eddie Hung
2019-11-21
1
-1
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+1
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
Eddie Hung
2019-11-21
5
-16
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+55
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Add a equiv test too
Eddie Hung
2019-11-19
2
-0
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+23
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Add two tests
Eddie Hung
2019-11-19
1
-0
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+12
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abc9 to support async flops $_DFF_[NP][NP][01]_
Eddie Hung
2019-11-19
1
-1
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+2
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