iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added ModWalker helper class	Clifford Wolf	2014-07-19	1	-0/+298
*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19	1	-4/+4
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	2	-4/+36
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	3	-10/+264
*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18	1	-1/+3
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18	1	-2/+2
*	added tests/memories	Clifford Wolf	2014-07-18	5	-0/+133
*	Added memory_share	Clifford Wolf	2014-07-18	3	-0/+266
*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18	1	-0/+1
*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18	1	-0/+15
*	Added function-like cell creation helpers	Clifford Wolf	2014-07-18	2	-73/+158
*	Added log_id() helper function	Clifford Wolf	2014-07-18	1	-0/+8
*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17	1	-1/+1
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	2	-3/+66
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	2	-0/+30
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	2	-9/+56
*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17	1	-5/+18
*	Fixed RTLIL::SigSpec::append_bit() for appending constants	Clifford Wolf	2014-07-17	1	-2/+3
*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17	1	-1/+1
*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17	1	-1/+4
*	Added "inout" ports support to read_liberty	Clifford Wolf	2014-07-16	1	-1/+6
*	Set blackbox attribute in "read_liberty -lib"	Clifford Wolf	2014-07-16	1	-0/+3
*	Fixed spelling of "direction" in read_liberty messages	Clifford Wolf	2014-07-16	1	-2/+2
*	Merged new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	10	-82/+216
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\| *	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	1	-2/+13
\| *	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16	1	-0/+80
\| *	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	2	-7/+6
\| *	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	3	-38/+56
\| *	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16	1	-30/+55
\| *	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16	2	-5/+6
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*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16	5	-5/+15
*	Added passing of various options to vhdl2verilog	Clifford Wolf	2014-07-12	1	-5/+36
*	Use "verilog -sv" to parse .sv files	Clifford Wolf	2014-07-11	1	-0/+2
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11	1	-0/+5
*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05	3	-4/+43
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	2	-0/+14
*	small changes in presentation	Clifford Wolf	2014-07-02	1	-5/+2
*	Tiny fix in presentation	Clifford Wolf	2014-06-29	1	-1/+1
*	Progress in presentation	Clifford Wolf	2014-06-29	2	-0/+97
*	Added links to some liberty files to README	Clifford Wolf	2014-06-28	1	-0/+8
*	Progress in presentation	Clifford Wolf	2014-06-26	7	-79/+105
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25	2	-3/+22
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24	1	-6/+6
*	Progress in presentation	Clifford Wolf	2014-06-22	7	-42/+503
*	Little steps in realmath test bench	Clifford Wolf	2014-06-21	2	-2/+8
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21	1	-2/+8
*	fixed typo	Clifford Wolf	2014-06-21	1	-1/+1
*	Progress in presentation	Clifford Wolf	2014-06-21	9	-23/+188