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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-182-12/+22
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve A/B reg packingEddie Hung2019-07-182-6/+11
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not autoremove A/B registers since they might have other consumersEddie Hung2019-07-181-2/+0
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrong wildcard symbolEddie Hung2019-07-181-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-172-5/+11
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::remove_const() to return SigSpec&Eddie Hung2019-07-172-2/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed extensionEddie Hung2019-07-162-6/+6
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si...David Shah2019-07-162-4/+8
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support {A,B,P}REG packingEddie Hung2019-07-162-55/+94
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::extract to allow negative lengthEddie Hung2019-07-161-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::extend_u0() to return *thisEddie Hung2019-07-152-2/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Oops forgot these filesEddie Hung2019-07-153-2/+12
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add xilinx_dsp for register packingEddie Hung2019-07-153-2/+192
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Tidy upEddie Hung2019-07-151-39/+26
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1516-30/+639
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1034-271/+734
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-084-7/+77
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-085-2/+280
* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix "scc" call inside abc9 to consider all wiresEddie Hung2019-09-291-1/+1
* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-297-9/+12
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1413 from YosysHQ/mmicko/backend_binary_outMiodrag Milanović2019-09-295-7/+7
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add aiger and protobuf backends binary supportMiodrag Milanovic2019-09-282-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support binary files for backends, fixes #1407Miodrag Milanovic2019-09-283-4/+4
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