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| * | | | | | | | | | | | | | | | | Use -map instead of -symbols for aigerEddie Hung2019-04-121-2/+3
| * | | | | | | | | | | | | | | | | ci_bits and co_bits now a list, order is important for ABCEddie Hung2019-04-121-24/+34
| * | | | | | | | | | | | | | | | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
| * | | | | | | | | | | | | | | | | WIPEddie Hung2019-04-121-14/+68
| * | | | | | | | | | | | | | | | | Comment outEddie Hung2019-04-121-1/+1
| * | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-122-1/+14
| * | | | | | | | | | | | | | | | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
| * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| | * | | | | | | | | | | | | | | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
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| | | * | | | | | | | | | | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | * | | | | | | | | | | | | | | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | * | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
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* | | | | | | | | | | | | | | | | PI before CIEddie Hung2019-04-121-2/+2
* | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-121-3/+9
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| * | | | | | | | | | | | | | | | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
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| | * | | | | | | | | | | | | | | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | | | | | | | | | | | | | | | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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* | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-111-1/+0
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| * | | | | | | | | | | | | | | | More unusedEddie Hung2019-04-111-1/+0
* | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-116-8/+93
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| * | | | | | | | | | | | | | | | Remove unusedEddie Hung2019-04-111-1/+0
| * | | | | | | | | | | | | | | | FixesEddie Hung2019-04-111-20/+16
| * | | | | | | | | | | | | | | | WIPEddie Hung2019-04-112-0/+89
| * | | | | | | | | | | | | | | | Spelling fixesEddie Hung2019-04-111-2/+2
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| * | | | | | | | | | | | | | | Add default entry to testcaseEddie Hung2019-04-111-2/+3
| * | | | | | | | | | | | | | | Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * | | | | | | | | | | | | | Fix a few typosEddie Hung2019-04-081-3/+3
* | | | | | | | | | | | | | | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
* | | | | | | | | | | | | | | More fine tuningEddie Hung2019-04-111-2/+2
* | | | | | | | | | | | | | | Fix cells_map.vEddie Hung2019-04-111-7/+7
* | | | | | | | | | | | | | | Fix typoEddie Hung2019-04-111-1/+1
* | | | | | | | | | | | | | | Juggle opt calls in synth_xilinxEddie Hung2019-04-112-30/+35
* | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-1/+1
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| * | | | | | | | | | | | | | Add non-input bits driven by unrecognised cells as ci_bitsEddie Hung2019-04-101-1/+1
* | | | | | | | | | | | | | | WIP for cells_map.v -- maybe working?Eddie Hung2019-04-101-32/+27
* | | | | | | | | | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1Eddie Hung2019-04-101-31/+38
* | | | | | | | | | | | | | | Fix for when B_SIGNED = 1Eddie Hung2019-04-101-1/+8
* | | | | | | | | | | | | | | Update doc for synth_xilinxEddie Hung2019-04-101-7/+8
* | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-24/+21
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| * | | | | | | | | | | | | | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
* | | | | | | | | | | | | | | ff_map.v after abcEddie Hung2019-04-101-5/+5
* | | | | | | | | | | | | | | Tidy upEddie Hung2019-04-101-1/+1
* | | | | | | | | | | | | | | Move map_cells to before map_lutsEddie Hung2019-04-101-11/+12
* | | | | | | | | | | | | | | WIP for $shiftx to wide muxEddie Hung2019-04-101-1/+63
* | | | | | | | | | | | | | | Update LUT delaysEddie Hung2019-04-101-11/+8
* | | | | | | | | | | | | | | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
* | | | | | | | | | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
* | | | | | | | | | | | | | | Add delays to cells.boxEddie Hung2019-04-091-4/+12
* | | | | | | | | | | | | | | Add "-lut <file>" support to abc9Eddie Hung2019-04-091-13/+31
* | | | | | | | | | | | | | | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-21 18:14:10 +0000