| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fixed the help summary line for a few commands | acw1251 | 2019-06-19 | 4 | -6/+6 |
| * | Fix bug in #1078, add entry to CHANGELOG | Eddie Hung | 2019-06-19 | 2 | -3/+4 |
| * | Merge pull request #1109 from YosysHQ/clifford/fix1106 | Clifford Wolf | 2019-06-19 | 6 | -9/+48 |
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| | * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 6 | -9/+48 |
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| * | Merge pull request #1105 from YosysHQ/clifford/fixlogicinit | Clifford Wolf | 2019-06-19 | 5 | -16/+92 |
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| | * | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
| | * | Use input default values in hierarchy pass | Clifford Wolf | 2019-06-19 | 1 | -0/+38 |
| | * | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 2 | -0/+15 |
| | * | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
| * | | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
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| * | Merge pull request #1100 from bwidawsk/home | Clifford Wolf | 2019-06-19 | 5 | -0/+8 |
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| | * | Support filename rewrite in backends | Ben Widawsky | 2019-06-18 | 4 | -0/+4 |
| | * | Support ~ for home directory | Ben Widawsky | 2019-06-18 | 1 | -0/+4 |
| * | | Merge pull request #1104 from whitequark/case-semantics | Clifford Wolf | 2019-06-19 | 2 | -1/+40 |
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| | * | Explain exact semantics of switch and case rules in the manual. | whitequark | 2019-06-19 | 1 | -0/+12 |
| | * | In RTLIL::Module::check(), check process invariants. | whitequark | 2019-06-19 | 1 | -1/+28 |
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| * | Merge pull request #1086 from udif/pr_elab_sys_tasks2 | Clifford Wolf | 2019-06-18 | 2 | -3/+13 |
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| | * | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 2 | -3/+13 |
| * | | Add timescale and generated-by header to yosys-smtbmc MkVcd | Clifford Wolf | 2019-06-16 | 1 | -0/+2 |
| * | | Merge pull request #829 from abdelrahmanhosny/master | Serge Bazanski | 2019-06-13 | 2 | -0/+46 |
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| | * | address review comments | Abdelrahman | 2019-03-01 | 1 | -23/+9 |
| | * | add dockerignore file | Abdelrahman | 2019-02-26 | 1 | -0/+13 |
| | * | dockerize yosys | Abdelrahman | 2019-02-26 | 1 | -0/+47 |
| * | | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
| * | | Merge pull request #1082 from corecode/u4k | David Shah | 2019-06-10 | 1 | -0/+24 |
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| | * | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 |
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| * | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs | Clifford Wolf | 2019-06-08 | 1 | -12/+42 |
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| | * | | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 |
| * | | | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 |
| * | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger | Clifford Wolf | 2019-06-07 | 27 | -45/+128 |
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| | * | | | Add read_aiger to CHANGELOG | Eddie Hung | 2019-06-07 | 1 | -0/+1 |
| | * | | | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 |
| | * | | | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 |
| | * | | | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
| | * | | | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 |
| | * | | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
| | * | | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
| | * | | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
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| * | | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 |
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| | * | | | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 4 | -50/+38 |
| | * | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 10 | -5/+107 |
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| | | * | | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 10 | -5/+107 |
| * | | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 |
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| * | | | | Merge branch 'tux3-implicit_named_connection' | Clifford Wolf | 2019-06-07 | 4 | -3/+40 |
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| | * | | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 3 | -13/+2 |
| | * | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 5 | -4/+52 |
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| | | * | | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 5 | -12/+59 |
| * | | | | | Merge pull request #1076 from thasti/centos7-build-fix | Clifford Wolf | 2019-06-07 | 1 | -1/+0 |
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| | * | | | | remove boost/log/exceptions.hpp from wrapper generator | Stefan Biereigel | 2019-06-07 | 1 | -1/+0 |
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| * | | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 |
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