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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-11-211-1/+6
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add multi clock testEddie Hung2019-11-201-0/+5
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix INIT valuesEddie Hung2019-11-201-4/+4
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-19228-24028/+35109
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0814-138/+539
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-10-071-7/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename $currQ to $abc9_currQEddie Hung2019-10-072-54/+54
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of latch_* in write_xaigerEddie Hung2019-10-071-7/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove "write_xaiger -zinit"Eddie Hung2019-10-071-16/+6
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comment on default flop initEddie Hung2019-10-071-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of output_port lookupEddie Hung2019-10-071-14/+8
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-056-308/+276
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Error if $currQ not foundEddie Hung2019-10-051-0/+4
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | abc -> abc9Eddie Hung2019-10-041-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix from mergeEddie Hung2019-10-041-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-048-184/+33
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix merge issuesEddie Hung2019-10-046-21/+14
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0434-361/+376
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0320-86/+374
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EnglishEddie Hung2019-10-031-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More fixesEddie Hung2019-10-011-16/+16
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to punch ports at allEddie Hung2019-09-302-13/+24
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup $currQ from aigerparseEddie Hung2019-09-301-2/+0
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove need for $currQ port connectionEddie Hung2019-09-304-114/+129
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-09-301-100/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add commentEddie Hung2019-09-301-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a cell_cache to instantiate once rather than opt_merge callEddie Hung2019-09-301-15/+15
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scc call on active module module only, plus cleanupEddie Hung2019-09-302-29/+28
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use derived moduleEddie Hung2019-09-301-22/+5
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-3029-132/+1981
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missing endmoduleEddie Hung2019-09-291-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2945-281/+6242
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix "scc" call inside abc9 to consider all wiresEddie Hung2019-09-291-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-297-9/+12
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-289-441/+485
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use abc_mergeability attr for "r" extensionEddie Hung2019-09-271-58/+66
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split ABC9 based on clocking only, add "abc_mergeability" attr for enEddie Hung2019-09-271-88/+28
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix infinite recursionEddie Hung2019-09-271-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 18:15:24 +0000