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* Add "read -undef"Clifford Wolf2018-06-281-0/+32
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-06-201-1/+1
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| * Merge pull request #572 from q3k/q3k/fix-protobuf-buildClifford Wolf2018-06-201-1/+1
| |\ | | | | | | Fix protobuf build
| | * Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
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* / Add automatic verific import in hierarchy commandClifford Wolf2018-06-203-1/+75
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #571 from q3k/q3k/protobuf-backendClifford Wolf2018-06-195-0/+560
|\ | | | | Add Protobuf backend
| * Add Protobuf backendSerge Bazanski2018-06-195-0/+560
| | | | | | | | Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
* | Be slightly less aggressive in "deminout" passClifford Wolf2018-06-191-4/+28
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #570 from edcote/patch-4Clifford Wolf2018-06-191-4/+4
|\ \ | |/ |/| Include module name for area summary stats
| * Include module name for area summary statsEdmond Cote2018-06-181-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
* Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #561 from udif/pr_skip_typoClifford Wolf2018-06-061-1/+1
|\ | | | | Fixed typo (sikp -> skip)
| * Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
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* Add (* gclk *) attribute supportClifford Wolf2018-06-014-1/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add setundef -anyseq / -anyconst support to -undriven modeClifford Wolf2018-06-011-3/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "setundef -anyconst"Clifford Wolf2018-06-011-20/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in handling of array instances with empty portsClifford Wolf2018-05-311-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update examples/cmos/counter.ys to use "synth" commandClifford Wolf2018-05-301-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update ABC to git rev 6df1396Clifford Wolf2018-05-301-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some cleanup code to memory_nordffClifford Wolf2018-05-281-26/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add comment to VIPER #13453 work-aroundClifford Wolf2018-05-281-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #454 from rqou/emscripten-and-abcClifford Wolf2018-05-194-15/+87
|\ | | | | Add option to statically link abc; emscripten fixes
| * Force abc to align memory to 8 bytesRobert Ou2018-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | Apparently abc has a memory pool implementation that by default returns memory that is unaligned. There is a workaround in the abc makefile that uses uname to look for "arm" specifically and then sets the alignment. However, ARM is not the only platform that requires proper alignment (e.g. emscripten does too). For now, pessimistically force the alignment for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten despite being approximately a 32-bit platform).
| * Modify emscripten main to mount nodefs and to run arg as a scriptRobert Ou2018-05-181-1/+18
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| * Force abc to be linked statically and without threads in emscriptenRobert Ou2018-05-181-0/+5
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| * Fix infinite loop in abc command under emscriptenRobert Ou2018-05-181-5/+7
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| * Fix reading techlibs under emscriptenRobert Ou2018-05-181-1/+1
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| * Add options to disable abc's usage of pthreads and readlineRobert Ou2018-05-181-0/+10
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| * Add an option to statically link abc into yosysRobert Ou2018-05-182-4/+38
| | | | | | | | This is currently incomplete because the output filter no longer works.
| * Makefile: Make abc always use stdint.hRobert Ou2018-05-181-4/+8
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* Merge pull request #550 from jimparis/yosys-upstreamClifford Wolf2018-05-171-1/+6
|\ | | | | Support SystemVerilog `` extension for macros
| * Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
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| * Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
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* | Merge pull request #551 from olofk/ice40_cells_sim_portsClifford Wolf2018-05-171-43/+23
|\ \ | |/ |/| Avoid mixing module port declaration styles in ice40 cells_sim.v
| * Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
|/ | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove mercurial from build instructionsClifford Wolf2018-05-151-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix iopadmap for loops between tristate IO buffersClifford Wolf2018-05-151-0/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix iopadmap for cases where IO pins already have buffers on themClifford Wolf2018-05-151-1/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Some cleanups in setundef.ccClifford Wolf2018-05-131-0/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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