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| * | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| * | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
* | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
* | | Add paramsEddie Hung2019-07-181-0/+6
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| | * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| | * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| | * | synth_intel: revert change to run_max10Dan Ravensloft2019-07-181-1/+1
| | * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-182-29/+11
| | * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| * | | Merge pull request #1207 from ZirconiumX/intel_new_pass_namesDavid Shah2019-07-181-4/+4
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| | * | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1828-195/+387
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| * | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| | * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| | * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
| * | | Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| | * | | write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| * | | | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
| * | | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
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| | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| * | | | Merge pull request #1202 from YosysHQ/cmp2lut_lut6Eddie Hung2019-07-164-24/+37
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| | * | | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
| | * | | Forgot to commitEddie Hung2019-07-161-0/+7
| | * | | Add tests for cmp2lut on LUT6Eddie Hung2019-07-162-23/+29
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| * | | Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-162-45/+128
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| | * | | Add commentEddie Hung2019-07-131-0/+5
| | * | | Update test with more accurate LUT maskEddie Hung2019-07-121-1/+1
| | * | | duplicate -> cloneEddie Hung2019-07-121-3/+3
| | * | | More cleanupEddie Hung2019-07-121-8/+2
| | * | | CleanupEddie Hung2019-07-121-29/+51
| | * | | CleanupEddie Hung2019-07-121-10/+4
| | * | | CleanupEddie Hung2019-07-121-15/+24
| | * | | More cleanupEddie Hung2019-07-121-11/+10
| | * | | CleanupEddie Hung2019-07-121-46/+16
| | * | | CleanupEddie Hung2019-07-121-7/+1
| | * | | CleanupEddie Hung2019-07-121-13/+109
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| * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-169-31/+122
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| | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
| | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
| | * | | Do not double count cells in abcEddie Hung2019-07-121-2/+2
| | * | | Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
| | * | | Off by oneEddie Hung2019-07-121-1/+1
| | * | | Fix spacingEddie Hung2019-07-121-1/+1
| | * | | Remove double pushEddie Hung2019-07-121-1/+0