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| * memory_map: Add -formal optionJannis Harder2022-08-162-17/+68
| | | | | | | | | | | | This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.
| * setundef: Do not add anyseq / anyconst to unused memory port clocksJannis Harder2022-08-161-0/+24
| | | | | | | | Instead set those unused clocks to zero.
| * wreduce: Keep more x-bits with -keepdcJannis Harder2022-08-161-4/+4
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| * formalff: New -setundef optionJannis Harder2022-08-161-0/+335
| | | | | | | | | | | | | | Find FFs with undefined initialization values for which changing the initialization does not change the observable behavior and initialize them. For -ff2anyinit, this reduces the number of generated $anyinit cells that drive wires with private names.
| * formalff: Set new replaced_by_gclk attribute on removed dff's clksJannis Harder2022-08-164-0/+44
| | | | | | | | | | | | This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute.
| * Add the $anyinit cell and the formalff passJannis Harder2022-08-1616-8/+271
|/ | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Bump versiongithub-actions[bot]2022-08-121-1/+1
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* Merge pull request #3425 from YosysHQ/lofty/stat-jsonN. Engelhardt2022-08-111-38/+109
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| * stat: add option for machine-readable json outputLofty2022-08-111-38/+109
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* | Merge pull request #3277 from YosysHQ/lofty/rename-scramble_nameN. Engelhardt2022-08-112-0/+87
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| * rename: add -scramble-name option to randomly rename selectionsLofty2022-08-082-0/+87
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* | Bump versiongithub-actions[bot]2022-08-111-1/+1
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* | Merge pull request #3443 from YosysHQ/micko/resetall_undefineallMiodrag Milanović2022-08-101-0/+5
|\ \ | | | | | | resetall does not affect text defines, but undefineall does
| * | set default_nettype to wire for resetallMiodrag Milanovic2022-08-101-0/+1
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| * | resetall does not affect text defines, but undefineall doesMiodrag Milanovic2022-08-101-0/+4
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* | Merge pull request #3322 from Forty-Bot/default_assignment_firstN. Engelhardt2022-08-101-10/+38
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| * | Order ports with default assignments firstSean Anderson2022-08-091-10/+38
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Although the current style is allowed by the standard, Icarus verilog doesn't parse default assignments using an implicit net type: techlibs/ice40/cells_sim.v:305: syntax error techlibs/ice40/cells_sim.v:1: Errors in port declarations. Fix this by making sure that ports with default assignments first on their line. Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models") Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | Bump versiongithub-actions[bot]2022-08-101-1/+1
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* | nexus: Fix BRAM mapping.Marcelina Kościelnicka2022-08-091-18/+56
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* | Merge pull request #3441 from YosysHQ/micko/smtio-utf-8Miodrag Milanović2022-08-091-2/+2
|\ \ | | | | | | Switched to utf-8 in smtio.py
| * | Switched to utf-8 in smtio.pyMiodrag Milanovic2022-08-091-2/+2
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* | properly encode string in rtlilMiodrag Milanovic2022-08-091-1/+1
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* | Bump versiongithub-actions[bot]2022-08-091-1/+1
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* | Merge pull request #3439 from YosysHQ/micko/filepath_improveMiodrag Milanović2022-08-0810-60/+90
|\ \ | |/ |/| File path encoding improvements
| * support file locations containing spacesMiodrag Milanovic2022-08-086-18/+19
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| * Encode filename unprintable charsMiodrag Milanovic2022-08-084-27/+42
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| * verific - make filepath handling compatible with verilog frontendMiodrag Milanovic2022-08-081-15/+29
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* Bump versiongithub-actions[bot]2022-08-041-1/+1
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* Next dev cycleMiodrag Milanovic2022-08-032-2/+5
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* Release version 0.20Miodrag Milanovic2022-08-032-3/+3
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* Update ChangelogMiodrag Milanovic2022-08-031-0/+7
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* update manual to latestMiodrag Milanovic2022-08-031-2/+5
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* Merge pull request #3432 from YosysHQ/aki/jny_updatesMiodrag Milanović2022-08-032-10/+226
|\ | | | | jny: Added JNY schema and additional information to JNY output file
| * misc: Added JNY schema definitionAki Van Ness2022-08-021-0/+193
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| * backend: jny: updated the `JnyWriter` to emite a new "invocation" entry as ↵Aki Van Ness2022-08-021-10/+33
| | | | | | | | well as a "$schema" entry to point to the location the schema will be at
* | Update manual and changelogMiodrag Milanovic2022-08-032-0/+9
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* | Bump versiongithub-actions[bot]2022-08-031-1/+1
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* | Merge pull request #3433 from jix/fix_smt_shiftJannis Harder2022-08-021-4/+4
|\ \ | |/ |/| smt2: Fix $shift/$shiftx with negative shift ammounts
| * smt2: Fix $shift/$shiftx with negative shift ammountsJannis Harder2022-08-021-4/+4
|/ | | | Fixes #3431, fixes #3344
* Bump versiongithub-actions[bot]2022-08-021-1/+1
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* Merge pull request #3089 from YosysHQ/gatecat/liberty_wbMiodrag Milanović2022-08-011-0/+14
|\ | | | | Add read_liberty -wb
| * Add read_liberty -wbgatecat2021-11-251-0/+14
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #3429 from YosysHQ/micko/verific_uptoMiodrag Milanović2022-08-011-2/+5
|\ \ | | | | | | Setting wire upto in verific import
| * | Setting wire upto in verific importMiodrag Milanovic2022-07-291-2/+5
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* | | Update documentationMiodrag Milanovic2022-08-011-0/+4
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* | Bump versiongithub-actions[bot]2022-07-291-1/+1
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* | Update READMEMiodrag Milanović2022-07-281-1/+1
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* | Bump versiongithub-actions[bot]2022-07-281-1/+1
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* | Assorted microoptimization speedups in core data structures.Marcelina Kościelnicka2022-07-276-193/+117
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* | macos 10.15 deprecated by gh actionsMiodrag Milanovic2022-07-271-54/+0
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