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* Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-187-75/+72
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| * Update to ABC d1b6413Clifford Wolf2019-04-171-1/+1
| * Merge pull request #939 from YosysHQ/revert895Eddie Hung2019-04-161-28/+0
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| | * Revert #895Eddie Hung2019-04-161-28/+0
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| * Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
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| | * Revert "Recognise default entry in case even if all cases covered (fix for #9...Eddie Hung2019-04-152-4/+3
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| * Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
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| | * README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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| * Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
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| | * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| * | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
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| | * | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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| | * Add default entry to testcaseEddie Hung2019-04-111-2/+3
| | * Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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* | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
* | Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"Eddie Hung2019-04-101-2/+0
* | Revert ""&nf -D 0" fails => use "-D 1" instead"Eddie Hung2019-04-101-1/+1
* | Merge remote-tracking branch 'origin/master' into eddie/fix_retimeEddie Hung2019-04-102-4/+5
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| * Fix a few typosEddie Hung2019-04-081-3/+3
| * Merge pull request #919 from YosysHQ/multiport_transpClifford Wolf2019-04-081-1/+2
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| | * memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
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* | Add retime testEddie Hung2019-04-051-0/+6
* | Fix S0 -> S1Eddie Hung2019-04-051-1/+1
* | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
* | RetryEddie Hung2019-04-051-1/+1
* | "&nf -D 0" fails => use "-D 1" insteadEddie Hung2019-04-051-1/+1
* | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
* | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
* | abc -dff now implies "-D 0" otherwise retiming doesn't happenEddie Hung2019-04-051-0/+2
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* Add "read_ilang -lib"Clifford Wolf2019-04-055-3/+39
* Added missing argument checking to "mutate" commandClifford Wolf2019-04-041-0/+32
* Merge pull request #913 from smunaut/fix_proc_muxEddie Hung2019-04-031-1/+1
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| * proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
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* Merge pull request #912 from YosysHQ/bram_addr_enClifford Wolf2019-04-031-0/+2
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| * memory_bram: Consider read enable for address expansion registerDavid Shah2019-04-021-0/+2
* | Merge pull request #910 from ucb-bar/memupdatesClifford Wolf2019-04-031-30/+173
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| * Refine memory support to deal with general Verilog memory definitions.Jim Lawson2019-04-011-30/+173
* | Merge pull request #895 from YosysHQ/pmux2shiftxEddie Hung2019-04-021-0/+28
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| * Create one $shiftx per bit in widthEddie Hung2019-03-251-10/+17
| * Add a pmux-to-shiftx optimisation to proc_muxEddie Hung2019-03-231-0/+21
* | Merge pull request #907 from YosysHQ/clifford/fix906Clifford Wolf2019-03-301-0/+2
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| * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
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* | Merge pull request #901 from trcwm/libertyfixesClifford Wolf2019-03-284-9/+151
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| * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
| * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
| * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-274-9/+151
* | | Merge pull request #903 from YosysHQ/bram_reset_transpClifford Wolf2019-03-281-0/+1
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