| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | ecp5: Add blackboxes for ancillary DCU cells | David Shah | 2018-11-09 | 1 | -0/+18 | |
| | | * | | | | | | | ecp5: Adding some blackbox cells | David Shah | 2018-11-07 | 2 | -1/+391 | |
| * | | | | | | | | | Update ABC to git rev 68da3cf | Clifford Wolf | 2018-11-11 | 1 | -1/+1 | |
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| * | | | | | | | | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 | |
| * | | | | | | | | Merge pull request #696 from arjenroodselaar/verific_darwin | Clifford Wolf | 2018-11-09 | 1 | -0/+4 | |
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| | * | | | | | | | | Use appropriate static libraries when building with Verific on MacOS | Arjen Roodselaar | 2018-11-07 | 1 | -0/+4 | |
| * | | | | | | | | | Fix "make ystests" to use correct Yosys binary | Clifford Wolf | 2018-11-08 | 1 | -1/+1 | |
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| * | | | | | | | | Merge pull request #693 from YosysHQ/rlimit | Clifford Wolf | 2018-11-07 | 1 | -8/+11 | |
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| | * | | | | | | | | Limit stack size to 16 MB on Darwin | Clifford Wolf | 2018-11-07 | 1 | -1/+4 | |
| | * | | | | | | | | Fix for improved smtio.py rlimit code | Clifford Wolf | 2018-11-06 | 1 | -1/+1 | |
| | * | | | | | | | | Improve stack rlimit code in smtio.py | Clifford Wolf | 2018-11-06 | 1 | -8/+8 | |
| * | | | | | | | | | Merge pull request #694 from trcwm/dffmap_expr_fix | Clifford Wolf | 2018-11-06 | 1 | -1/+10 | |
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| | * | | | | | | | | | DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/... | Niels Moseley | 2018-11-06 | 1 | -1/+10 | |
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| * | | | | | | | | | Run solver in non-incremental mode whem smtio.py is configured for non-increm... | Clifford Wolf | 2018-11-06 | 1 | -3/+12 | |
| * | | | | | | | | | Update ABC rev to 4d56acf | Clifford Wolf | 2018-11-06 | 1 | -1/+1 | |
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| * | | | | | | | | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 2 | -3/+4 | |
| * | | | | | | | | Merge pull request #691 from arjenroodselaar/stacksize | Clifford Wolf | 2018-11-05 | 1 | -1/+6 | |
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| | * | | | | | | | | Use conservative stack size for SMT2 on MacOS | Arjen Roodselaar | 2018-11-04 | 1 | -1/+6 | |
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| * | | | | | | | | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 | |
| * | | | | | | | | Add proper error message for when smtbmc "append" fails | Clifford Wolf | 2018-11-04 | 1 | -2/+10 | |
| * | | | | | | | | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 3 | -99/+69 | |
| * | | | | | | | | Merge pull request #687 from trcwm/master | Clifford Wolf | 2018-11-04 | 2 | -4/+10 | |
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| | * | | | | | | | | Liberty file newline handling is more relaxed. More descriptive error message | Niels Moseley | 2018-11-03 | 1 | -4/+7 | |
| | * | | | | | | | | Report an error when a liberty file contains pin references that reference no... | Niels Moseley | 2018-11-03 | 1 | -0/+3 | |
| * | | | | | | | | | Merge pull request #688 from ZipCPU/rosenfell | Clifford Wolf | 2018-11-04 | 1 | -2/+8 | |
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| | * | | | | | | | | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 | |
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| * | | | | | | | | Do not generate "reg assigned in a continuous assignment" warnings for "rand ... | Clifford Wolf | 2018-11-01 | 1 | -2/+15 | |
| * | | | | | | | | Add support for signed $shift/$shiftx in smt2 back-end | Clifford Wolf | 2018-11-01 | 1 | -1/+3 | |
| * | | | | | | | | Merge branch 'igloo2' | Clifford Wolf | 2018-10-31 | 5 | -0/+377 | |
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| | * | | | | | | | | Fix sf2 LUT interface | Clifford Wolf | 2018-10-31 | 2 | -12/+12 | |
| | * | | | | | | | | Basic SmartFusion2 and IGLOO2 synthesis support | Clifford Wolf | 2018-10-31 | 5 | -0/+377 | |
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| * | | | | | | | | Merge pull request #680 from jburgess777/fix-empty-string-back-assert | Clifford Wolf | 2018-10-30 | 1 | -1/+1 | |
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| | * | | | | | | | Avoid assert when label is an empty string | Jon Burgess | 2018-10-28 | 1 | -1/+1 | |
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| * | | | | | | | Merge pull request #678 from whentze/master | Clifford Wolf | 2018-10-25 | 1 | -2/+2 | |
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| | * | | | | | | | fix unhandled std::out_of_range when calling yosys with 3-character argument | whentze | 2018-10-22 | 1 | -2/+2 | |
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| * | | | | | | | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 | |
| * | | | | | | | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 14 | -14/+78 | |
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| | * | | | | | | | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 14 | -14/+78 | |
| * | | | | | | | | Merge pull request #677 from daveshah1/ecp5_dsp | Clifford Wolf | 2018-10-23 | 3 | -1/+97 | |
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| | * | | | | | | | ecp5: Remove DSP parameters that don't work | David Shah | 2018-10-22 | 1 | -21/+0 | |
| | * | | | | | | | ecp5: Add DSP blackboxes | David Shah | 2018-10-21 | 3 | -1/+118 | |
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| * | | | | | | | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 | |
| * | | | | | | | Merge pull request #674 from rubund/feature/svinterface_at_top | Clifford Wolf | 2018-10-20 | 11 | -70/+599 | |
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| | * | | | | | | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 4 | -136/+113 | |
| | * | | | | | | Support for SystemVerilog interfaces as a port in the top level module + test... | Ruben Undheim | 2018-10-20 | 9 | -10/+561 | |
| | * | | | | | | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 | |
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| * | | | | | | Merge pull request #673 from daveshah1/ecp5_improve | Clifford Wolf | 2018-10-19 | 4 | -6/+17 | |
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| | * | | | | | | ecp5: Sim model fixes | David Shah | 2018-10-19 | 1 | -3/+5 | |
| | * | | | | | | ecp5: Add latch inference | David Shah | 2018-10-19 | 3 | -3/+12 | |
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| * | | | | | | Merge pull request #672 from daveshah1/fix_bram | Clifford Wolf | 2018-10-19 | 1 | -0/+1 | |
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index : iCE40/yosys | |
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