diff options
Diffstat (limited to 'tests')
43 files changed, 850 insertions, 683 deletions
diff --git a/tests/asicworld/README b/tests/asicworld/README index 0e96edb7b..4657e7a27 100644 --- a/tests/asicworld/README +++ b/tests/asicworld/README @@ -1 +1 @@ -Borrowed verilog examples from http://www.asic-world.com/. +Borrowed Verilog examples from http://www.asic-world.com/. diff --git a/tests/asicworld/code_hdl_models_arbiter.v b/tests/asicworld/code_hdl_models_arbiter.v index 978e1987b..d3e3a66f1 100644 --- a/tests/asicworld/code_hdl_models_arbiter.v +++ b/tests/asicworld/code_hdl_models_arbiter.v @@ -1,123 +1,123 @@ -//----------------------------------------------------
-// A four level, round-robin arbiter. This was
-// orginally coded by WD Peterson in VHDL.
-//----------------------------------------------------
-module arbiter (
- clk,
- rst,
- req3,
- req2,
- req1,
- req0,
- gnt3,
- gnt2,
- gnt1,
- gnt0
-);
-// --------------Port Declaration-----------------------
-input clk;
-input rst;
-input req3;
-input req2;
-input req1;
-input req0;
-output gnt3;
-output gnt2;
-output gnt1;
-output gnt0;
-
-//--------------Internal Registers----------------------
-wire [1:0] gnt ;
-wire comreq ;
-wire beg ;
-wire [1:0] lgnt ;
-wire lcomreq ;
-reg lgnt0 ;
-reg lgnt1 ;
-reg lgnt2 ;
-reg lgnt3 ;
-reg lasmask ;
-reg lmask0 ;
-reg lmask1 ;
-reg ledge ;
-
-//--------------Code Starts Here-----------------------
-always @ (posedge clk)
-if (rst) begin
- lgnt0 <= 0;
- lgnt1 <= 0;
- lgnt2 <= 0;
- lgnt3 <= 0;
-end else begin
- lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
- | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
- | (~lcomreq & lmask1 & lmask0 & req0 )
- | ( lcomreq & lgnt0 );
- lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
- | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
- | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
- | ( lcomreq & lgnt1);
- lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
- | (~lcomreq & ~lmask1 & lmask0 & req2)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
- | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
- | ( lcomreq & lgnt2);
- lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
- | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
- | (~lcomreq & lmask1 & ~lmask0 & req3)
- | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
- | ( lcomreq & lgnt3);
-end
-
-//----------------------------------------------------
-// lasmask state machine.
-//----------------------------------------------------
-assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
-always @ (posedge clk)
-begin
- lasmask <= (beg & ~ledge & ~lasmask);
- ledge <= (beg & ~ledge & lasmask)
- | (beg & ledge & ~lasmask);
-end
-
-//----------------------------------------------------
-// comreq logic.
-//----------------------------------------------------
-assign lcomreq = ( req3 & lgnt3 )
- | ( req2 & lgnt2 )
- | ( req1 & lgnt1 )
- | ( req0 & lgnt0 );
-
-//----------------------------------------------------
-// Encoder logic.
-//----------------------------------------------------
-assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
-
-//----------------------------------------------------
-// lmask register.
-//----------------------------------------------------
-always @ (posedge clk )
-if( rst ) begin
- lmask1 <= 0;
- lmask0 <= 0;
-end else if(lasmask) begin
- lmask1 <= lgnt[1];
- lmask0 <= lgnt[0];
-end else begin
- lmask1 <= lmask1;
- lmask0 <= lmask0;
-end
-
-assign comreq = lcomreq;
-assign gnt = lgnt;
-//----------------------------------------------------
-// Drive the outputs
-//----------------------------------------------------
-assign gnt3 = lgnt3;
-assign gnt2 = lgnt2;
-assign gnt1 = lgnt1;
-assign gnt0 = lgnt0;
-
-endmodule
+//---------------------------------------------------- +// A four level, round-robin arbiter. This was +// orginally coded by WD Peterson in VHDL. +//---------------------------------------------------- +module arbiter ( + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 +); +// --------------Port Declaration----------------------- +input clk; +input rst; +input req3; +input req2; +input req1; +input req0; +output gnt3; +output gnt2; +output gnt1; +output gnt0; + +//--------------Internal Registers---------------------- +wire [1:0] gnt ; +wire comreq ; +wire beg ; +wire [1:0] lgnt ; +wire lcomreq ; +reg lgnt0 ; +reg lgnt1 ; +reg lgnt2 ; +reg lgnt3 ; +reg lasmask ; +reg lmask0 ; +reg lmask1 ; +reg ledge ; + +//--------------Code Starts Here----------------------- +always @ (posedge clk) +if (rst) begin + lgnt0 <= 0; + lgnt1 <= 0; + lgnt2 <= 0; + lgnt3 <= 0; +end else begin + lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) + | (~lcomreq & lmask1 & lmask0 & req0 ) + | ( lcomreq & lgnt0 ); + lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req1 & ~req0) + | ( lcomreq & lgnt1); + lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req2) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0) + | ( lcomreq & lgnt2); + lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2) + | (~lcomreq & lmask1 & ~lmask0 & req3) + | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) + | ( lcomreq & lgnt3); +end + +//---------------------------------------------------- +// lasmask state machine. +//---------------------------------------------------- +assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; +always @ (posedge clk) +begin + lasmask <= (beg & ~ledge & ~lasmask); + ledge <= (beg & ~ledge & lasmask) + | (beg & ledge & ~lasmask); +end + +//---------------------------------------------------- +// comreq logic. +//---------------------------------------------------- +assign lcomreq = ( req3 & lgnt3 ) + | ( req2 & lgnt2 ) + | ( req1 & lgnt1 ) + | ( req0 & lgnt0 ); + +//---------------------------------------------------- +// Encoder logic. +//---------------------------------------------------- +assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)}; + +//---------------------------------------------------- +// lmask register. +//---------------------------------------------------- +always @ (posedge clk ) +if( rst ) begin + lmask1 <= 0; + lmask0 <= 0; +end else if(lasmask) begin + lmask1 <= lgnt[1]; + lmask0 <= lgnt[0]; +end else begin + lmask1 <= lmask1; + lmask0 <= lmask0; +end + +assign comreq = lcomreq; +assign gnt = lgnt; +//---------------------------------------------------- +// Drive the outputs +//---------------------------------------------------- +assign gnt3 = lgnt3; +assign gnt2 = lgnt2; +assign gnt1 = lgnt1; +assign gnt0 = lgnt0; + +endmodule diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v index 5e7bf46b9..78d1168e6 100644 --- a/tests/asicworld/code_hdl_models_arbiter_tb.v +++ b/tests/asicworld/code_hdl_models_arbiter_tb.v @@ -1,11 +1,11 @@ module testbench (); -reg clk; -reg rst; -reg req3; -reg req2; -reg req1; -reg req0; +reg clk = 0; +reg rst = 1; +reg req3 = 0; +reg req2 = 0; +reg req1 = 0; +reg req0 = 0; wire gnt3; wire gnt2; wire gnt1; @@ -13,17 +13,15 @@ wire gnt0; // Clock generator always #1 clk = ~clk; +integer file; + +always @(posedge clk) + $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0}); initial begin - $dumpfile ("arbiter.vcd"); - $dumpvars(); - clk = 0; - rst = 1; - req0 = 0; - req1 = 0; - req2 = 0; - req3 = 0; - #10 rst = 0; + file = $fopen(`outfile); + repeat (5) @ (posedge clk); + rst <= 0; repeat (1) @ (posedge clk); req0 <= 1; repeat (1) @ (posedge clk); diff --git a/tests/asicworld/code_hdl_models_dlatch_reset.v b/tests/asicworld/code_hdl_models_dlatch_reset.v deleted file mode 100644 index 2cfc6fbd8..000000000 --- a/tests/asicworld/code_hdl_models_dlatch_reset.v +++ /dev/null @@ -1,30 +0,0 @@ -//----------------------------------------------------- -// Design Name : dlatch_reset -// File Name : dlatch_reset.v -// Function : DLATCH async reset -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module dlatch_reset ( -data , // Data Input -en , // LatchInput -reset , // Reset input -q // Q output -); -//-----------Input Ports--------------- -input data, en, reset ; - -//-----------Output Ports--------------- -output q; - -//------------Internal Variables-------- -reg q; - -//-------------Code Starts Here--------- -always @ ( en or reset or data) -if (~reset) begin - q <= 1'b0; -end else if (en) begin - q <= data; -end - -endmodule //End Of Module dlatch_reset diff --git a/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v b/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v deleted file mode 100644 index d3338f749..000000000 --- a/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v +++ /dev/null @@ -1,58 +0,0 @@ -//----------------------------------------------------- -// Design Name : ram_sp_ar_sw -// File Name : ram_sp_ar_sw.v -// Function : Asynchronous read write RAM -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module ram_sp_ar_sw ( -clk , // Clock Input -address , // Address Input -data , // Data bi-directional -cs , // Chip Select -we , // Write Enable/Read Enable -oe // Output Enable -); - -parameter DATA_WIDTH = 8 ; -parameter ADDR_WIDTH = 8 ; -parameter RAM_DEPTH = 1 << ADDR_WIDTH; - -//--------------Input Ports----------------------- -input clk ; -input [ADDR_WIDTH-1:0] address ; -input cs ; -input we ; -input oe ; - -//--------------Inout Ports----------------------- -inout [DATA_WIDTH-1:0] data ; - -//--------------Internal variables---------------- -reg [DATA_WIDTH-1:0] data_out ; -reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - -//--------------Code Starts Here------------------ - -// Tri-State Buffer control -// output : When we = 0, oe = 1, cs = 1 -assign data = (cs && oe && !we) ? data_out : 8'bz; - -// Memory Write Block -// Write Operation : When we = 1, cs = 1 -always @ (posedge clk) -begin : MEM_WRITE - if ( cs && we ) begin - mem[address] = data; - end -end - -// Memory Read Block -// Read Operation : When we = 0, oe = 1, cs = 1 -always @ (address or cs or we or oe) -begin : MEM_READ - if (cs && !we && oe) begin - data_out = mem[address]; - end -end - -endmodule // End of Module ram_sp_ar_sw diff --git a/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v b/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v deleted file mode 100644 index c7fd9554d..000000000 --- a/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v +++ /dev/null @@ -1,62 +0,0 @@ -//----------------------------------------------------- -// Design Name : ram_sp_sr_sw -// File Name : ram_sp_sr_sw.v -// Function : Synchronous read write RAM -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module ram_sp_sr_sw ( -clk , // Clock Input -address , // Address Input -data , // Data bi-directional -cs , // Chip Select -we , // Write Enable/Read Enable -oe // Output Enable -); - -parameter DATA_WIDTH = 8 ; -parameter ADDR_WIDTH = 8 ; -parameter RAM_DEPTH = 1 << ADDR_WIDTH; - -//--------------Input Ports----------------------- -input clk ; -input [ADDR_WIDTH-1:0] address ; -input cs ; -input we ; -input oe ; - -//--------------Inout Ports----------------------- -inout [DATA_WIDTH-1:0] data ; - -//--------------Internal variables---------------- -reg [DATA_WIDTH-1:0] data_out ; -reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; -reg oe_r; - -//--------------Code Starts Here------------------ - -// Tri-State Buffer control -// output : When we = 0, oe = 1, cs = 1 -assign data = (cs && oe && !we) ? data_out : 8'bz; - -// Memory Write Block -// Write Operation : When we = 1, cs = 1 -always @ (posedge clk) -begin : MEM_WRITE - if ( cs && we ) begin - mem[address] = data; - end -end - -// Memory Read Block -// Read Operation : When we = 0, oe = 1, cs = 1 -always @ (posedge clk) -begin : MEM_READ - if (cs && !we && oe) begin - data_out = mem[address]; - oe_r = 1; - end else begin - oe_r = 0; - end -end - -endmodule // End of Module ram_sp_sr_sw diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v index 1bff66af8..5a7e0eaff 100644 --- a/tests/asicworld/code_hdl_models_t_gate_switch.v +++ b/tests/asicworld/code_hdl_models_t_gate_switch.v @@ -1,11 +1,11 @@ -module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule
+module t_gate_switch (L,R,nC,C); + inout L; + inout R; + input nC; + input C; + + //Syntax: keyword unique_name (drain. source, gate); + pmos p1 (L,R,nC); + nmos p2 (L,R,C); + +endmodule diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index ffe670994..e05302182 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -2,7 +2,7 @@ // Design Name : up_counter // File Name : up_counter.v // Function : Up counter -// Coder : Deepak +// Coder : Deepak //----------------------------------------------------- module up_counter ( out , // Output of the counter diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v index 534519745..10ca00df4 100644 --- a/tests/asicworld/code_verilog_tutorial_counter.v +++ b/tests/asicworld/code_verilog_tutorial_counter.v @@ -1,19 +1,19 @@ -//-----------------------------------------------------
-// Design Name : counter
-// File Name : counter.v
-// Function : 4 bit up counter
-// Coder : Deepak
-//-----------------------------------------------------
-module counter (clk, reset, enable, count);
-input clk, reset, enable;
-output [3:0] count;
-reg [3:0] count;
-
-always @ (posedge clk)
-if (reset == 1'b1) begin
- count <= 0;
-end else if ( enable == 1'b1) begin
- count <= count + 1;
-end
-
-endmodule
+//----------------------------------------------------- +// Design Name : counter +// File Name : counter.v +// Function : 4 bit up counter +// Coder : Deepak +//----------------------------------------------------- +module counter (clk, reset, enable, count); +input clk, reset, enable; +output [3:0] count; +reg [3:0] count; + +always @ (posedge clk) +if (reset == 1'b1) begin + count <= 0; +end else if ( enable == 1'b1) begin + count <= count + 1; +end + +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v index 104779381..33d540509 100644 --- a/tests/asicworld/code_verilog_tutorial_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v @@ -1,113 +1,101 @@ -///////////////////////////////////////////////////////////////////////////
-// MODULE : counter_tb //
-// TOP MODULE : -- //
-// //
-// PURPOSE : 4-bit up counter test bench //
-// //
-// DESIGNER : Deepak Kumar Tala //
-// //
-// Revision History //
-// //
-// DEVELOPMENT HISTORY : //
-// Rev0.0 : Jan 03, 2003 //
-// Initial Revision //
-// //
-///////////////////////////////////////////////////////////////////////////
-module testbench;
-
-reg clk, reset, enable;
-wire [3:0] count;
-reg dut_error;
-
-counter U0 (
-.clk (clk),
-.reset (reset),
-.enable (enable),
-.count (count)
-);
-
-event reset_enable;
-event terminate_sim;
-
-initial
-begin
- $display ("###################################################");
- clk = 0;
- reset = 0;
- enable = 0;
- dut_error = 0;
-end
-
-always
- #5 clk = !clk;
-
-initial
-begin
- $dumpfile ("counter.vcd");
- $dumpvars;
-end
-
-
-initial
-@ (terminate_sim) begin
- $display ("Terminating simulation");
- if (dut_error == 0) begin
- $display ("Simulation Result : PASSED");
- end
- else begin
- $display ("Simulation Result : FAILED");
- end
- $display ("###################################################");
- #1 $finish;
-end
-
-
-
-event reset_done;
-
-initial
-forever begin
- @ (reset_enable);
- @ (negedge clk)
- $display ("Applying reset");
- reset = 1;
- @ (negedge clk)
- reset = 0;
- $display ("Came out of Reset");
- -> reset_done;
-end
-
-initial begin
- #10 -> reset_enable;
- @ (reset_done);
- @ (negedge clk);
- enable = 1;
- repeat (5)
- begin
- @ (negedge clk);
- end
- enable = 0;
- #5 -> terminate_sim;
-end
-
-
-reg [3:0] count_compare;
-
-always @ (posedge clk)
-if (reset == 1'b1)
- count_compare <= 0;
-else if ( enable == 1'b1)
- count_compare <= count_compare + 1;
-
-
-
-always @ (negedge clk)
-if (count_compare != count) begin
- $display ("DUT ERROR AT TIME%d",$time);
- $display ("Expected value %d, Got Value %d", count_compare, count);
- dut_error = 1;
- #5 -> terminate_sim;
-end
-
-endmodule
-
+/////////////////////////////////////////////////////////////////////////// +// MODULE : counter_tb // +// TOP MODULE : -- // +// // +// PURPOSE : 4-bit up counter test bench // +// // +// DESIGNER : Deepak Kumar Tala // +// // +// Revision History // +// // +// DEVELOPMENT HISTORY : // +// Rev0.0 : Jan 03, 2003 // +// Initial Revision // +// // +/////////////////////////////////////////////////////////////////////////// +module testbench; + +integer file; +reg clk = 0, reset = 0, enable = 0; +wire [3:0] count; +reg dut_error = 0; + +counter U0 ( +.clk (clk), +.reset (reset), +.enable (enable), +.count (count) +); + +event reset_enable; +event terminate_sim; + +initial + file = $fopen(`outfile); + +always + #5 clk = !clk; + +initial +@ (terminate_sim) begin + $fdisplay (file, "Terminating simulation"); + if (dut_error == 0) begin + $fdisplay (file, "Simulation Result : PASSED"); + end + else begin + $fdisplay (file, "Simulation Result : FAILED"); + end + $fdisplay (file, "###################################################"); + #1 $finish; +end + + + +event reset_done; + +initial +forever begin + @ (reset_enable); + @ (negedge clk) + $fdisplay (file, "Applying reset"); + reset = 1; + @ (negedge clk) + reset = 0; + $fdisplay (file, "Came out of Reset"); + -> reset_done; +end + +initial begin + #10 -> reset_enable; + @ (reset_done); + @ (negedge clk); + enable = 1; + repeat (5) + begin + @ (negedge clk); + end + enable = 0; + #5 -> terminate_sim; +end + + +reg [3:0] count_compare; + +always @ (posedge clk) +if (reset == 1'b1) + count_compare <= 0; +else if ( enable == 1'b1) + count_compare <= count_compare + 1; + + + +always @ (negedge clk) +if (count_compare != count) begin + $fdisplay (file, "DUT ERROR AT TIME%d",$time); + $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count); + dut_error = 1; + #5 -> terminate_sim; +end + +endmodule + diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v index f065732be..806e17736 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v @@ -1,16 +1,13 @@ module testbench(); // Declare inputs as regs and outputs as wires -reg clock, reset, enable; +reg clock = 1, reset = 0, enable = 0; wire [3:0] counter_out; +integer file; // Initialize all variables initial begin - $display ("time\t clk reset enable counter"); - $monitor ("%g\t %b %b %b %b", - $time, clock, reset, enable, counter_out); - clock = 1; // initial value of clock - reset = 0; // initial value of reset - enable = 0; // initial value of enable + file = $fopen(`outfile); + $fdisplay (file, "time\t clk reset enable counter"); #5 reset = 1; // Assert the reset #10 reset = 0; // De-assert the reset #10 enable = 1; // Assert enable @@ -18,6 +15,10 @@ initial begin #5 $finish; // Terminate simulation end +always @(negedge clock) + $fdisplay (file, "%g\t %b %b %b %b", + $time, clock, reset, enable, counter_out); + // Clock generator initial begin #1; diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index 2e9448950..a8e15568b 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -1,14 +1,14 @@ module testbench(); -reg clock , reset ; +reg clock = 0 , reset ; reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; +integer file; initial begin // $dumpfile("testbench.vcd"); // $dumpvars(0, testbench); - $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3"); - $monitor("%g\t %b %b %b %b %b %b %b %b", - $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + file = $fopen(`outfile); + $fdisplay(file, "Time\t R0 R1 R2 R3 G0 G1 G2 G3"); clock = 0; reset = 1; req_0 = 0; @@ -28,6 +28,10 @@ initial begin #10 $finish; end +always @(negedge clock) + $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", + $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + initial begin #1; forever diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 2adfdcfb0..05a7ed027 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -1,7 +1,4 @@ -#!/usr/bin/python - -from __future__ import division -from __future__ import print_function +#!/usr/bin/env python3 import os import sys @@ -250,10 +247,10 @@ print("Rng seed: %d" % seed) random.seed(seed) for k1 in range(5): - dsc_f = file("temp/brams_%02d.txt" % k1, "w") - sim_f = file("temp/brams_%02d.v" % k1, "w") - ref_f = file("temp/brams_%02d_ref.v" % k1, "w") - tb_f = file("temp/brams_%02d_tb.v" % k1, "w") + dsc_f = open("temp/brams_%02d.txt" % k1, "w") + sim_f = open("temp/brams_%02d.v" % k1, "w") + ref_f = open("temp/brams_%02d_ref.v" % k1, "w") + tb_f = open("temp/brams_%02d_tb.v" % k1, "w") for f in [sim_f, ref_f, tb_f]: print("`timescale 1 ns / 1 ns", file=f) diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh index d617187ec..f0bf0131e 100755 --- a/tests/bram/run-test.sh +++ b/tests/bram/run-test.sh @@ -8,7 +8,7 @@ rm -rf temp mkdir -p temp echo "generating tests.." -python generate.py +python3 generate.py { echo -n "all:" diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py index b5b4626df..8757d4741 100644 --- a/tests/fsm/generate.py +++ b/tests/fsm/generate.py @@ -1,7 +1,4 @@ -#!/usr/bin/python - -from __future__ import division -from __future__ import print_function +#!/usr/bin/env python3 import sys import random @@ -34,76 +31,78 @@ def random_expr(variables): raise AssertionError for idx in range(50): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - rst2 = random.choice([False, True]) - if rst2: - print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) - print(' input clk, rst1, rst2;') - print(' output rst;') - print(' assign rst = rst1 || rst2;') - else: - print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx)) - print(' input clk, rst;') - variables=['a', 'b', 'c', 'x', 'y', 'z'] - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31))) - state_bits = random.randint(5, 16); - print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', - '(* fsm_encoding = "binary" *)']), state_bits-1)) - states=[] - for i in range(random.randint(2, 10)): - n = random.randint(0, 2**state_bits-1) - if n not in states: - states.append(n) - print(' always @(posedge clk) begin') - print(' if (%s) begin' % ('rst1' if rst2 else 'rst')) - print(' x <= %d;' % random.randint(0, 2**31-1)) - print(' y <= %d;' % random.randint(0, 2**31-1)) - print(' z <= %d;' % random.randint(0, 2**31-1)) - print(' state <= %d;' % random.choice(states)) - print(' end else begin') - print(' case (state)') - for state in states: - print(' %d: begin' % state) - for var in ('x', 'y', 'z'): - print(' %s <= %s;' % (var, random_expr(variables))) - next_states = states[:] - for i in range(random.randint(0, len(states))): - next_state = random.choice(next_states) - next_states.remove(next_state) - print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables), - random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state)) - print(' end') - print(' endcase') - if rst2: - print(' if (rst2) begin') - print(' x <= a;') - print(' y <= b;') - print(' z <= c;') - print(' state <= %d;' % random.choice(states)) - print(' end') - print(' end') - print(' end') - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - if test_verific: - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;; rename uut_%05d gold' % idx) - print('verific -vlog2k temp/uut_%05d.v' % idx) - print('verific -import uut_%05d' % idx) - print('rename uut_%05d gate' % idx) - else: - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;;') - print('copy uut_%05d gold' % idx) - print('rename uut_%05d gate' % idx) - print('cd gate') - print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive'])) - print('cd ..') - print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) - + with open('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + rst2 = random.choice([False, True]) + if rst2: + print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst1, rst2;') + print(' output rst;') + print(' assign rst = rst1 || rst2;') + else: + print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst;') + variables=['a', 'b', 'c', 'x', 'y', 'z'] + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31))) + state_bits = random.randint(5, 16); + print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', + '(* fsm_encoding = "binary" *)']), state_bits-1)) + states=[] + for i in range(random.randint(2, 10)): + n = random.randint(0, 2**state_bits-1) + if n not in states: + states.append(n) + print(' always @(posedge clk) begin') + print(' if (%s) begin' % ('rst1' if rst2 else 'rst')) + print(' x <= %d;' % random.randint(0, 2**31-1)) + print(' y <= %d;' % random.randint(0, 2**31-1)) + print(' z <= %d;' % random.randint(0, 2**31-1)) + print(' state <= %d;' % random.choice(states)) + print(' end else begin') + print(' case (state)') + for state in states: + print(' %d: begin' % state) + for var in ('x', 'y', 'z'): + print(' %s <= %s;' % (var, random_expr(variables))) + next_states = states[:] + for i in range(random.randint(0, len(states))): + next_state = random.choice(next_states) + next_states.remove(next_state) + print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables), + random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state)) + print(' end') + print(' endcase') + if rst2: + print(' if (rst2) begin') + print(' x <= a;') + print(' y <= b;') + print(' z <= c;') + print(' state <= %d;' % random.choice(states)) + print(' end') + print(' end') + print(' end') + print('endmodule') + with open('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + if test_verific: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;; rename uut_%05d gold' % idx) + print('verific -vlog2k temp/uut_%05d.v' % idx) + print('verific -import uut_%05d' % idx) + print('rename uut_%05d gate' % idx) + else: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('cd gate') + print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive'])) + print('cd ..') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) + diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh index 57c2a5b12..423892334 100755 --- a/tests/fsm/run-test.sh +++ b/tests/fsm/run-test.sh @@ -8,7 +8,7 @@ set -e rm -rf temp mkdir -p temp echo "generating tests.." -python generate.py +python3 generate.py { all_targets="all_targets:" diff --git a/tests/hana/README b/tests/hana/README index b2a08fd47..2081fb10f 100644 --- a/tests/hana/README +++ b/tests/hana/README @@ -1,4 +1,4 @@ -This test cases are copied from the hana project: +These test cases are copied from the hana project: https://sourceforge.net/projects/sim-sim/ diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py index 972021dc8..19d01c7c6 100644 --- a/tests/realmath/generate.py +++ b/tests/realmath/generate.py @@ -1,7 +1,4 @@ -#!/usr/bin/python - -from __future__ import division -from __future__ import print_function +#!/usr/bin/env python3 import sys import random @@ -39,53 +36,56 @@ def random_expression(depth = 3, maxparam = 0): return op + '(' + recursion() + ', ' + recursion() + ')' raise -for idx in range(100): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) - for i in range(30): - if idx < 10: - print('localparam p%02d = %s;' % (i, random_expression())) - else: - print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression())) - for i in range(30, 60): - if idx < 10: - print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) - else: - print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) - for i in range(100): - print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - print('read_verilog uut_%05d.v' % idx) - print('rename uut_%05d uut_%05d_syn' % (idx, idx)) - print('write_verilog uut_%05d_syn.v' % idx) - with file('temp/uut_%05d_tb.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d_tb;\n' % idx) - print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) - print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) - print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) - print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) - print('task compare_ref_syn;') - print(' input [7:0] i;') - print(' input [63:0] r, s;') - print(' reg [64*8-1:0] buffer;') - print(' integer j;') - print(' begin') - print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') - print(' // $display("%d: %b %b", i, r, s);') - print(' end else if (r === s) begin ') - print(' // $display("%d: %b %b", i, r, s);') - print(' end else begin ') - print(' for (j = 0; j < 64; j = j+1)') - print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') - print(' $display("\\n%3d: %b %b", i, r, s);') - print(' $display(" %s %s", buffer, buffer);') - print(' end') - print(' end') - print('endtask') - print('initial begin #1;') - for i in range(100): - print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) - print('end') - print('endmodule') - +for idx in range(100): + with open('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) + for i in range(30): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression())) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression())) + for i in range(30, 60): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) + for i in range(100): + print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) + print('endmodule') + with open('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog uut_%05d.v' % idx) + print('rename uut_%05d uut_%05d_syn' % (idx, idx)) + print('write_verilog uut_%05d_syn.v' % idx) + with open('temp/uut_%05d_tb.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d_tb;\n' % idx) + print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) + print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) + print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) + print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) + print('task compare_ref_syn;') + print(' input [7:0] i;') + print(' input [63:0] r, s;') + print(' reg [64*8-1:0] buffer;') + print(' integer j;') + print(' begin') + print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else if (r === s) begin ') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else begin ') + print(' for (j = 0; j < 64; j = j+1)') + print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') + print(' $display("\\n%3d: %b %b", i, r, s);') + print(' $display(" %s %s", buffer, buffer);') + print(' end') + print(' end') + print('endtask') + print('initial begin #1;') + for i in range(100): + print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) + print('end') + print('endmodule') + diff --git a/tests/realmath/run-test.sh b/tests/realmath/run-test.sh index 0997ccb5d..f1ec5476b 100755 --- a/tests/realmath/run-test.sh +++ b/tests/realmath/run-test.sh @@ -4,7 +4,7 @@ set -e rm -rf temp mkdir -p temp echo "generating tests.." -python generate.py +python3 generate.py cd temp echo "running tests.." @@ -15,7 +15,7 @@ for ((i = 0; i < 100; i++)); do iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v ./uut_${idx}_tb | tee uut_${idx}.err if test -s uut_${idx}.err; then - echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog." + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." exit 1 fi rm -f uut_${idx}.err diff --git a/tests/share/generate.py b/tests/share/generate.py index a06a642d8..01a19a8d9 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -1,7 +1,4 @@ -#!/usr/bin/python - -from __future__ import division -from __future__ import print_function +#!/usr/bin/env python3 import sys import random @@ -25,49 +22,51 @@ def maybe_plus_x(expr): return expr for idx in range(100): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - if random.choice(['bin', 'uni']) == 'bin': - print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) - op = random.choice([ - random.choice(['+', '-', '*', '/', '%']), - random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), - random.choice(['<<', '>>', '<<<', '>>>']), - random.choice(['|', '&', '^', '~^', '||', '&&']), - ]) - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input s;') - print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % - (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), - random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), - random_plus_x() if random.randint(0, 4) == 0 else '')) - print('endmodule') - else: - print('module uut_%05d(a, b, x, s, y);' % (idx)) - op = random.choice(['~', '-', '!']) - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input s;') - print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % - (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), - random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), - random_plus_x() if random.randint(0, 4) == 0 else '')) - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;;') - print('copy uut_%05d gold' % idx) - print('rename uut_%05d gate' % idx) - print('tee -a temp/all_share_log.txt log') - print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) - print('tee -a temp/all_share_log.txt wreduce') - print('tee -a temp/all_share_log.txt share -aggressive gate') - print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') - + with open('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + if random.choice(['bin', 'uni']) == 'bin': + print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % + (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), + random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + else: + print('module uut_%05d(a, b, x, s, y);' % (idx)) + op = random.choice(['~', '-', '!']) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % + (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), + random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + with open('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt wreduce') + print('tee -a temp/all_share_log.txt share -aggressive gate') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') + diff --git a/tests/share/run-test.sh b/tests/share/run-test.sh index 6e880677c..18dbbc279 100755 --- a/tests/share/run-test.sh +++ b/tests/share/run-test.sh @@ -8,7 +8,7 @@ set -e rm -rf temp mkdir -p temp echo "generating tests.." -python generate.py +python3 generate.py echo "running tests.." for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v new file mode 100644 index 000000000..d1d8be862 --- /dev/null +++ b/tests/simple/constmuldivmod.v @@ -0,0 +1,27 @@ +module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); + always @* begin + case (mode) + 0: Y = A / 8'd0; + 1: Y = A % 8'd0; + 2: Y = A * 8'd0; + + 3: Y = A / 8'd1; + 4: Y = A % 8'd1; + 5: Y = A * 8'd1; + + 6: Y = A / 8'd2; + 7: Y = A % 8'd2; + 8: Y = A * 8'd2; + + 9: Y = A / 8'd4; + 10: Y = A % 8'd4; + 11: Y = A * 8'd4; + + 12: Y = A / 8'd8; + 13: Y = A % 8'd8; + 14: Y = A * 8'd8; + + default: Y = 8'd16 * A; + endcase + end +endmodule diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v index 2f2737c4c..7765d6e2a 100644 --- a/tests/simple/dff_different_styles.v +++ b/tests/simple/dff_different_styles.v @@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin end endmodule -// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of +// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of // simulation-implementation mismatches. The following testcases try to cover the // part that is defined and avoid the undefined cases. diff --git a/tests/simple/graphtest.v b/tests/simple/graphtest.v new file mode 100644 index 000000000..74788dbbe --- /dev/null +++ b/tests/simple/graphtest.v @@ -0,0 +1,34 @@ +module graphtest (A,B,X,Y,Z); + +input [3:0] A; +input [3:0] B; +output reg [3:0] X; +output [9:0] Y; +output [7:0] Z; + +wire [4:0] t; + +assign t[4] = 1'b0; // Constant connects to wire +assign t[2:0] = A[2:0] & { 2'b10, B[3]}; // Concatenation of intermediate wire +assign t[3] = A[2] ^ B[3]; // Bitwise-XOR + +// assign Y[2:0] = 3'b111; +// assign Y[6:3] = A; +// assign Y[9:7] = t[0:2]; +assign Y = {3'b111, A, t[2:0]}; // Direct assignment of concatenation + +assign Z[0] = 1'b0; // Constant connects to PO +assign Z[1] = t[3]; // Intermediate sig connects to PO +assign Z[3:2] = A[2:1]; // PI connects to PO +assign Z[7:4] = {1'b0, B[2:0]}; // Concat of CV and PI connect to PO + +always @* begin + if (A == 4'b1111) begin // All-Const at port (eq) + X = B; + end + else begin + X = 4'b0000; // All-Const at port (mux) + end +end + +endmodule diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v index 17888009f..123afaeab 100644 --- a/tests/simple/hierarchy.v +++ b/tests/simple/hierarchy.v @@ -5,10 +5,10 @@ input [3:0] a; input signed [3:0] b; output [7:0] y1, y2, y3, y4; -// this version triggers a bug in icarus verilog +// this version triggers a bug in Icarus Verilog // submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4); -// this version is handled correctly by icarus verilog +// this version is handled correctly by Icarus Verilog submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4); endmodule diff --git a/tests/simple/loops.v b/tests/simple/loops.v index 77cdcd8e2..d7743a422 100644 --- a/tests/simple/loops.v +++ b/tests/simple/loops.v @@ -41,10 +41,10 @@ begin keysched_last_key_i = key_i; else keysched_last_key_i = keysched_new_key_o; - + if (round == 0 && addroundkey_start_i) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = key_i; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; @@ -66,7 +66,7 @@ begin end else if (addroundkey_round == round && keysched_ready_o) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = keysched_new_key_o; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index bed5528d4..b1ab04d62 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -19,9 +19,9 @@ endmodule // ------------------------------------------------------ -module mem2reg_test2(clk, mode, addr, data); +module mem2reg_test2(clk, reset, mode, addr, data); -input clk, mode; +input clk, reset, mode; input [2:0] addr; output [3:0] data; @@ -33,6 +33,10 @@ assign data = mem[addr]; integer i; always @(posedge clk) begin + if (reset) begin + for (i=0; i<8; i=i+1) + mem[i] <= i; + end else if (mode) begin for (i=0; i<8; i=i+1) mem[i] <= mem[i]+1; @@ -47,7 +51,7 @@ endmodule // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); -reg [7:0] dint_c [0:7]; +reg [7:0] dint_c [0:7]; always @(posedge clk) begin {dout_a[0], dint_c[3]} <= din_a; diff --git a/tests/simple/memory.v b/tests/simple/memory.v index db06c56d2..9fddce26c 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -205,3 +205,62 @@ module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); end endmodule +// ---------------------------------------------------------- + +module memtest09 ( + input clk, + input [3:0] a_addr, a_din, b_addr, b_din, + input a_wen, b_wen, + output reg [3:0] a_dout, b_dout +); + reg [3:0] memory [10:35]; + + always @(posedge clk) begin + if (a_wen) + memory[10 + a_addr] <= a_din; + a_dout <= memory[10 + a_addr]; + end + + always @(posedge clk) begin + if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen)) + memory[20 + b_addr] <= b_din; + b_dout <= memory[20 + b_addr]; + end +endmodule + +// ---------------------------------------------------------- + +module memtest10(input clk, input [5:0] din, output [5:0] dout); + reg [5:0] queue [0:3]; + integer i; + + always @(posedge clk) begin + queue[0] <= din; + for (i = 1; i < 4; i=i+1) begin + queue[i] <= queue[i-1]; + end + end + + assign dout = queue[3]; +endmodule + +// ---------------------------------------------------------- + +module memtest11(clk, wen, waddr, raddr, wdata, rdata); + input clk, wen; + input [1:0] waddr, raddr; + input [7:0] wdata; + output [7:0] rdata; + + reg [7:0] mem [3:0]; + + assign rdata = mem[raddr]; + + always @(posedge clk) begin + if (wen) + mem[waddr] <= wdata; + else + mem[waddr] <= mem[waddr]; + end +endmodule + diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v index dc8860dee..569a28adb 100644 --- a/tests/simple/omsp_dbg_uart.v +++ b/tests/simple/omsp_dbg_uart.v @@ -22,13 +22,13 @@ always @(uart_state or mem_burst) RX_DATA : uart_state_nxt = RX_SYNC; default : uart_state_nxt = RX_CMD; endcase - + always @(posedge dbg_clk or posedge dbg_rst) if (dbg_rst) uart_state <= RX_SYNC; else if (xfer_done | mem_burst) uart_state <= uart_state_nxt; assign cmd_valid = (uart_state==RX_CMD) & xfer_done; assign xfer_done = uart_state!=RX_SYNC; - + endmodule diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v index eb832e6f5..a2fe00055 100644 --- a/tests/simple/rotate.v +++ b/tests/simple/rotate.v @@ -1,5 +1,5 @@ -// test case taken from amber23 verilog code +// test case taken from amber23 Verilog code module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod); input [31:0] i_in; diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v index 9b8e26e51..fa50c1d5c 100644 --- a/tests/simple/task_func.v +++ b/tests/simple/task_func.v @@ -68,7 +68,7 @@ endmodule // ------------------------------------------------------------------- -module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); +module task_func_test03(input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); assign dout_a = test(din_a,din_b); function [7:0] test; input [7:0] a; @@ -80,3 +80,43 @@ module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout end endfunction endmodule + +// ------------------------------------------------------------------- + +module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4); + parameter p = 23; + parameter px = 42; + function [7:0] test1; + input [7:0] i; + parameter p = 42; + begin + test1 = i + p; + end + endfunction + function [7:0] test2; + input [7:0] i; + parameter p2 = p+42; + begin + test2 = i + p2; + end + endfunction + function [7:0] test3; + input [7:0] i; + begin + test3 = i + p; + end + endfunction + function [7:0] test4; + input [7:0] i; + parameter px = p + 13; + parameter p3 = px - 37; + parameter p4 = p3 ^ px; + begin + test4 = i + p4; + end + endfunction + assign out1 = test1(in); + assign out2 = test2(in); + assign out3 = test3(in); + assign out4 = test4(in); +endmodule diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index d1f55fdb4..3bb3cf992 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -27,14 +27,14 @@ module test04(a, y); assign y = ~(a - 1'b0); endmodule -// .. this test triggers a bug in xilinx isim. +// .. this test triggers a bug in Xilinx ISIM. // module test05(a, y); // input a; // output y; // assign y = 12345 >> {a, 32'd0}; // endmodule -// .. this test triggers a bug in icarus verilog. +// .. this test triggers a bug in Icarus Verilog. // module test06(a, b, c, y); // input signed [3:0] a; // input signed [1:0] b; diff --git a/tests/simple/wreduce.v b/tests/simple/wreduce.v new file mode 100644 index 000000000..ba5484385 --- /dev/null +++ b/tests/simple/wreduce.v @@ -0,0 +1,9 @@ +module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z); + assign x = -$signed({1'b0, a}); + assign y = $signed({1'b0, a}) + $signed({1'b0, b}); + assign z = x ^ y; +endmodule + +module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w); + assign x = a - b, y = a * b, z = a >> b, w = a << b; +endmodule diff --git a/tests/smv/.gitignore b/tests/smv/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/smv/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/smv/run-single.sh b/tests/smv/run-single.sh new file mode 100644 index 000000000..a261f4ea6 --- /dev/null +++ b/tests/smv/run-single.sh @@ -0,0 +1,33 @@ +#!/bin/bash + +cat > $1.tpl <<EOT +%module main + INVARSPEC ! bool(_trigger) +EOT + +cat > $1.ys <<EOT +echo on + +read_ilang $1.il +hierarchy; proc; opt +rename -top uut +design -save gold + +synth +design -stash gate + +design -copy-from gold -as gold uut +design -copy-from gate -as gate uut +miter -equiv -flatten gold gate main +hierarchy -top main + +dump +write_smv -tpl $1.tpl $1.smv +EOT + +set -ex + +../../yosys -l $1.log -q $1.ys +NuSMV -bmc $1.smv >> $1.log +grep "^-- invariant .* is true" $1.log + diff --git a/tests/smv/run-test.sh b/tests/smv/run-test.sh new file mode 100755 index 000000000..74a54486d --- /dev/null +++ b/tests/smv/run-test.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +set -ex + +rm -rf temp +mkdir -p temp + +../../yosys -p 'test_cell -muxdiv -w temp/test all' +rm -f temp/test_{alu,fa,lcu,lut,macc,shiftx}_* + +cat > temp/makefile << "EOT" +all: $(addsuffix .ok,$(basename $(wildcard temp/test_*.il))) +%.ok: %.il + bash run-single.sh $(basename $<) + touch $@ +EOT + +${MAKE:-make} -f temp/makefile + diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 820f89de4..762e2938e 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -1,10 +1,11 @@ -module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); +module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; parameter SIZE = 256; parameter OFFSET = 0; parameter ABITS = 8; parameter WIDTH = 8; + parameter signed INIT = 1'bx; parameter RD_PORTS = 1; parameter RD_CLK_ENABLE = 1'b1; @@ -16,6 +17,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter WR_CLK_POLARITY = 1'b1; input [RD_PORTS-1:0] RD_CLK; + input [RD_PORTS-1:0] RD_EN; input [RD_PORTS*ABITS-1:0] RD_ADDR; output reg [RD_PORTS*WIDTH-1:0] RD_DATA; @@ -29,6 +31,8 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter _TECHMAP_CONNMAP_RD_CLK_ = 0; parameter _TECHMAP_CONNMAP_WR_CLK_ = 0; + parameter _TECHMAP_CONSTVAL_RD_EN_ = 0; + parameter _TECHMAP_BITS_CONNMAP_ = 0; parameter _TECHMAP_CONNMAP_WR_EN_ = 0; @@ -37,10 +41,18 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); initial begin _TECHMAP_FAIL_ <= 0; + // no initialized memories + if (INIT !== 1'bx) + _TECHMAP_FAIL_ <= 1; + // only map cells with only one read and one write port if (RD_PORTS > 1 || WR_PORTS > 1) _TECHMAP_FAIL_ <= 1; + // read enable must be constant high + if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1) + _TECHMAP_FAIL_ <= 1; + // we expect positive read clock and non-transparent reads if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY) _TECHMAP_FAIL_ <= 1; diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 50f5cb580..82fecfd80 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -16,7 +16,7 @@ toolsdir="$(cd $(dirname $0); pwd)" warn_iverilog_git=false if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then - ( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 + ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi while getopts xmGl:wkjvref:s:p:n: opt; do @@ -56,28 +56,24 @@ while getopts xmGl:wkjvref:s:p:n: opt; do esac done -create_ref() { - cp "$1" "$2.v" -} - compile_and_run() { exe="$1"; output="$2"; shift 2 if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work - /opt/altera/$altver/modelsim_ase/bin/vlog "$@" - /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output" + /opt/altera/$altver/modelsim_ase/bin/vlog +define+outfile=\"$output\" "$@" + /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench elif $use_xsim; then ( set +x files=( "$@" ) xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) - /opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}" - /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output" + /opt/Xilinx/Vivado/$xilver/bin/xvlog -d outfile=\"$output\" "${files[@]}" + /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench ) else - iverilog -s testbench -o "$exe" "$@" - vvp -n "$exe" > "$output" + iverilog -Doutfile=\"$output\" -s testbench -o "$exe" "$@" + vvp -n "$exe" fi } @@ -108,15 +104,15 @@ do fn=$(basename $fn) bn=$(basename $bn) - cp ../$fn $fn + egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v + if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v $fn + "$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v else cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi - create_ref $fn ${bn}_ref - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 @@ -131,22 +127,22 @@ do test_count=$(( test_count + 1 )) } - if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then + if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then touch ../${bn}.skip return fi if [ -n "$scriptfiles" ]; then - test_passes $fn $scriptfiles + test_passes ${bn}_ref.v $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend" -p "$scriptopt" $fn + test_passes -f "$frontend" -p "$scriptopt" ${bn}_ref.v elif [ "$frontend" = "verific" ]; then - test_passes -p "verific -vlog2k $fn; verific -import -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then - test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn - test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn + test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v + test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v fi touch ../${bn}.log } @@ -168,7 +164,7 @@ do else echo "${status_prefix}-> ERROR!" if $warn_iverilog_git; then - echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog." + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." fi $keeprunning || exit 1 fi diff --git a/tests/tools/txt2tikztiming.py b/tests/tools/txt2tikztiming.py index cfefe339f..9c6cd3a19 100755 --- a/tests/tools/txt2tikztiming.py +++ b/tests/tools/txt2tikztiming.py @@ -1,7 +1,4 @@ -#!/usr/bin/python - -from __future__ import division -from __future__ import print_function +#!/usr/bin/env python3 import argparse import fileinput diff --git a/tests/tools/vcdcd.pl b/tests/tools/vcdcd.pl index 6f497e99c..58a92b44d 100755 --- a/tests/tools/vcdcd.pl +++ b/tests/tools/vcdcd.pl @@ -35,7 +35,7 @@ if ($#ARGV != 1) { print STDERR "Usage: $0 [-w N] [-d N] gold.vcd gate.vcd\n"; print STDERR "\n"; print STDERR " -w N\n"; - print STDERR " reserve N characters for bitmap in text ouput (default: auto)\n"; + print STDERR " reserve N characters for bitmap in text output (default: auto)\n"; print STDERR "\n"; print STDERR " -d N\n"; print STDERR " allow for N timesteps delay between gate and gold (default: 0)\n"; diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys new file mode 100644 index 000000000..7ac460f13 --- /dev/null +++ b/tests/various/muxcover.ys @@ -0,0 +1,51 @@ + +read_verilog -formal <<EOT + module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y); + always @* + (* parallel_case *) + casez (X) + 3'b??1: Y = A; + 3'b?1?: Y = B; + 3'b1??: Y = C; + 3'b000: Y = D; + endcase + endmodule +EOT + + +## Examle usage for "pmuxtree" and "muxcover" + +proc +pmuxtree +techmap +muxcover -mux4 + +splitnets -ports +clean +# show + + +## Equivalence checking + +read_verilog -formal <<EOT + module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y); + always @* + casez (X) + 3'b001: Y = A; + 3'b010: Y = B; + 3'b100: Y = C; + 3'b000: Y = D; + default: Y = 'bx; + endcase + endmodule +EOT + +proc +splitnets -ports +techmap -map +/simcells.v t:$_MUX4_ + +equiv_make gold gate equiv +hierarchy -top equiv +equiv_simple -undef +equiv_status -assert + diff --git a/tests/vloghtb/common.sh b/tests/vloghtb/common.sh index 3965b04ca..a8335c2bd 100644 --- a/tests/vloghtb/common.sh +++ b/tests/vloghtb/common.sh @@ -68,3 +68,39 @@ test_equiv() log_pass test_$1 $4 mv log_test_$1/$4.out log_test_$1/$4.txt } + +test_febe() +{ + # Usage: + # test_febe <test_name> <synth_script> <extension> <backend> <frontend> <sat_options> <mod_name> <vlog_file> + # $1 $2 $3 $4 $5 $6 $7 $8 + + mkdir -p log_test_$1 + rm -f log_test_$1/$7.txt + rm -f log_test_$1/$7.err + + if ! ../../yosys -q -l log_test_$1/$7.out - 2> /dev/null <<- EOT + echo on + read_verilog $8 + $2 + design -save gold + dump + $4 log_test_$1/$7$3 + design -reset + $5 log_test_$1/$7$3 + + design -copy-from gold -as gold $7 + rename $7 gate + + miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter + sat $6 -verify -prove trigger 0 -show-inputs -show-outputs miter + EOT + then + log_fail test_$1 $7 + mv log_test_$1/$7.out log_test_$1/$7.err + exit 1 + fi + + log_pass test_$1 $7 + mv log_test_$1/$7.out log_test_$1/$7.txt +} diff --git a/tests/vloghtb/test_febe.sh b/tests/vloghtb/test_febe.sh new file mode 100644 index 000000000..482d44d9a --- /dev/null +++ b/tests/vloghtb/test_febe.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +set -e +source common.sh + +f=$1 +n=$(basename ${f%.v}) + +test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f +test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f +test_febe blif "synth; splitnets -ports" ".blif" "write_blif" "read_blif" "-ignore_div_by_zero" $n $f + +exit 0 |