diff options
Diffstat (limited to 'tests')
38 files changed, 902 insertions, 0 deletions
diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v new file mode 100644 index 000000000..68e9b1d50 --- /dev/null +++ b/tests/errors/syntax_err01.v @@ -0,0 +1,4 @@ +module a; +integer [31:0]w; +endmodule + diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v new file mode 100644 index 000000000..c72e976a8 --- /dev/null +++ b/tests/errors/syntax_err02.v @@ -0,0 +1,7 @@ +module a; +task to ( + input integer [3:0]x +); +endtask +endmodule + diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v new file mode 100644 index 000000000..6eec44ade --- /dev/null +++ b/tests/errors/syntax_err03.v @@ -0,0 +1,7 @@ +module a; +task to ( + input [3]x +); +endtask +endmodule + diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v new file mode 100644 index 000000000..d488e5dbb --- /dev/null +++ b/tests/errors/syntax_err04.v @@ -0,0 +1,4 @@ +module a; +wire [3]x; +endmodule + diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v new file mode 100644 index 000000000..8a1f11532 --- /dev/null +++ b/tests/errors/syntax_err05.v @@ -0,0 +1,4 @@ +module a; +input x[2:0]; +endmodule + diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v new file mode 100644 index 000000000..b35a1dea2 --- /dev/null +++ b/tests/errors/syntax_err06.v @@ -0,0 +1,6 @@ +module a; +initial +begin : label1 +end: label2 +endmodule + diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v new file mode 100644 index 000000000..62bcc6b3e --- /dev/null +++ b/tests/errors/syntax_err07.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = (4)55; +endmodule + diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v new file mode 100644 index 000000000..d41bfd6c9 --- /dev/null +++ b/tests/errors/syntax_err08.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = x 55; +endmodule + diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v new file mode 100644 index 000000000..1e472eb94 --- /dev/null +++ b/tests/errors/syntax_err09.v @@ -0,0 +1,3 @@ +module a(input wire x = 1'b0); +endmodule + diff --git a/tests/errors/syntax_err10.v b/tests/errors/syntax_err10.v new file mode 100644 index 000000000..d3280405c --- /dev/null +++ b/tests/errors/syntax_err10.v @@ -0,0 +1,3 @@ +module a; +parameter integer [2:0]x=0; +endmodule diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v new file mode 100644 index 000000000..f3cde9dfc --- /dev/null +++ b/tests/errors/syntax_err11.v @@ -0,0 +1,3 @@ +module a; +parameter integer real x=0; +endmodule diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v new file mode 100644 index 000000000..f9b5d5b0b --- /dev/null +++ b/tests/errors/syntax_err12.v @@ -0,0 +1,7 @@ +interface iface; +endinterface + +module a ( + iface x = 1'b0 +); +endmodule diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v new file mode 100644 index 000000000..b5c942fca --- /dev/null +++ b/tests/errors/syntax_err13.v @@ -0,0 +1,4 @@ +module a #(p = 0) +(); +endmodule + diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/lut/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys new file mode 100644 index 000000000..dc0aaffc2 --- /dev/null +++ b/tests/lut/check_map.ys @@ -0,0 +1,4 @@ +simplemap +equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4 +design -load postopt +select -assert-count 1 t:$lut diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v new file mode 100644 index 000000000..68ae33fd6 --- /dev/null +++ b/tests/lut/map_and.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a&b; +endmodule diff --git a/tests/lut/map_mux.v b/tests/lut/map_mux.v new file mode 100644 index 000000000..ccecf3023 --- /dev/null +++ b/tests/lut/map_mux.v @@ -0,0 +1,5 @@ +module top(...); + input a, b, s; + output y; + assign y = s?a:b; +endmodule diff --git a/tests/lut/map_not.v b/tests/lut/map_not.v new file mode 100644 index 000000000..385997414 --- /dev/null +++ b/tests/lut/map_not.v @@ -0,0 +1,5 @@ +module top(...); + input a; + output y; + assign y = ~a; +endmodule diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v new file mode 100644 index 000000000..8b8c55188 --- /dev/null +++ b/tests/lut/map_or.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a|b; +endmodule diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v new file mode 100644 index 000000000..708a05789 --- /dev/null +++ b/tests/lut/map_xor.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a^b; +endmodule diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh new file mode 100644 index 000000000..207417fa6 --- /dev/null +++ b/tests/lut/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.v; do + echo "Running $x.." + ../../yosys -q -s check_map.ys -l ${x%.v}.log $x +done diff --git a/tests/opt/.gitignore b/tests/opt/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/opt/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/opt/opt_lut.v b/tests/opt/opt_lut.v new file mode 100644 index 000000000..b13db367d --- /dev/null +++ b/tests/opt/opt_lut.v @@ -0,0 +1,18 @@ +module top( + input [8:0] a, + input [8:0] b, + output [8:0] o1, + output [2:0] o2, + input [2:0] c, + input [2:0] d, + output [2:0] o3, + output [2:0] o4, + input s +); + +assign o1 = (s ? 0 : a + b); +assign o2 = (s ? a : a - b); +assign o3 = (s ? 4'b1111 : d + c); +assign o4 = (s ? d : c - d); + +endmodule diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys new file mode 100644 index 000000000..59b12c351 --- /dev/null +++ b/tests/opt/opt_lut.ys @@ -0,0 +1,4 @@ +read_verilog opt_lut.v +synth_ice40 +ice40_unlut +equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il new file mode 100644 index 000000000..7eb71890f --- /dev/null +++ b/tests/opt/opt_lut_port.il @@ -0,0 +1,18 @@ +module $1 + wire width 4 input 2 \_0_ + wire output 4 \_1_ + wire input 3 \_2_ + wire output 1 \o + cell $lut \_3_ + parameter \LUT 16'0011000000000011 + parameter \WIDTH 4 + connect \A { \_0_ [3] \o 2'00 } + connect \Y \_1_ + end + cell $lut \_4_ + parameter \LUT 4'0001 + parameter \WIDTH 4 + connect \A { 3'000 \_2_ } + connect \Y \o + end +end diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys new file mode 100644 index 000000000..51dfd988b --- /dev/null +++ b/tests/opt/opt_lut_port.ys @@ -0,0 +1,2 @@ +read_ilang opt_lut_port.il +select -assert-count 2 t:$lut diff --git a/tests/opt/run-test.sh b/tests/opt/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/opt/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done diff --git a/tests/svinterfaces/.gitignore b/tests/svinterfaces/.gitignore new file mode 100644 index 000000000..a5b7927d1 --- /dev/null +++ b/tests/svinterfaces/.gitignore @@ -0,0 +1,8 @@ +/a.out +/dut_result.txt +/reference_result.txt +/*.diff +/*.log_stderr +/*.log_stdout +/*_ref_syn.v +/*_syn.v diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh new file mode 100755 index 000000000..86567d1c1 --- /dev/null +++ b/tests/svinterfaces/run-test.sh @@ -0,0 +1,6 @@ +#/bin/bash -e + + + +./runone.sh svinterface1 +./runone.sh svinterface_at_top diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh new file mode 100755 index 000000000..0adecc797 --- /dev/null +++ b/tests/svinterfaces/runone.sh @@ -0,0 +1,44 @@ +#!/bin/bash + + +TESTNAME=$1 + +STDOUTFILE=${TESTNAME}.log_stdout +STDERRFILE=${TESTNAME}.log_stderr + +echo "" > $STDOUTFILE +echo "" > $STDERRFILE + +echo -n "Test: ${TESTNAME} -> " + +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE + +rm -f a.out reference_result.txt dut_result.txt + +set -e + +iverilog -g2012 ${TESTNAME}_syn.v +iverilog -g2012 ${TESTNAME}_ref_syn.v + +set +e +iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v +./a.out +mv output.txt reference_result.txt +if [ -f ${TESTNAME}_wrapper.v ] ; then + iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v +else + iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v +fi +./a.out +mv output.txt dut_result.txt + +diff reference_result.txt dut_result.txt > ${TESTNAME}.diff +RET=$? +if [ "$RET" != "0" ] ; then + echo "ERROR!" + exit -1 +fi + +echo "ok" +exit 0 diff --git a/tests/svinterfaces/svinterface1.sv b/tests/svinterfaces/svinterface1.sv new file mode 100644 index 000000000..6d60b4880 --- /dev/null +++ b/tests/svinterfaces/svinterface1.sv @@ -0,0 +1,117 @@ + + +module TopModule( + input logic clk, + input logic rst, + output logic [21:0] outOther, + input logic [1:0] sig, + input logic flip, + output logic [1:0] sig_out, + output logic [15:0] passThrough); + + MyInterface #(.WIDTH(4)) MyInterfaceInstance(); + + SubModule1 u_SubModule1 ( + .clk(clk), + .rst(rst), + .u_MyInterface(MyInterfaceInstance), + .outOther(outOther), + .sig (sig) + ); + + assign sig_out = MyInterfaceInstance.mysig_out; + + + assign MyInterfaceInstance.setting = flip; + + assign passThrough = MyInterfaceInstance.passThrough; + +endmodule + +interface MyInterface #( + parameter WIDTH = 3)( + ); + + logic setting; + logic [WIDTH-1:0] other_setting; + + logic [1:0] mysig_out; + + logic [15:0] passThrough; + + modport submodule1 ( + input setting, + output other_setting, + output mysig_out, + output passThrough + ); + + modport submodule2 ( + input setting, + output other_setting, + input mysig_out, + output passThrough + ); + +endinterface + + +module SubModule1( + input logic clk, + input logic rst, + MyInterface.submodule1 u_MyInterface, + input logic [1:0] sig, + output logic [21:0] outOther + + ); + + always_ff @(posedge clk or posedge rst) + if(rst) + u_MyInterface.mysig_out <= 0; + else begin + if(u_MyInterface.setting) + u_MyInterface.mysig_out <= sig; + else + u_MyInterface.mysig_out <= ~sig; + end + + MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub(); + + SubModule2 u_SubModule2 ( + .clk(clk), + .rst(rst), + .u_MyInterfaceInSub2(u_MyInterface), + .u_MyInterfaceInSub3(MyInterfaceInstanceInSub) + ); + + assign outOther = MyInterfaceInstanceInSub.other_setting; + + assign MyInterfaceInstanceInSub.setting = 0; + assign MyInterfaceInstanceInSub.mysig_out = sig; + +endmodule + +module SubModule2( + + input logic clk, + input logic rst, + MyInterface.submodule2 u_MyInterfaceInSub2, + MyInterface.submodule2 u_MyInterfaceInSub3 + + ); + + always_comb begin + if (u_MyInterfaceInSub3.mysig_out == 2'b00) + u_MyInterfaceInSub3.other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b01) + u_MyInterfaceInSub3.other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b10) + u_MyInterfaceInSub3.other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3.other_setting[21:0] = 4000; + end + + assign u_MyInterfaceInSub2.passThrough[7:0] = 124; + assign u_MyInterfaceInSub2.passThrough[15:8] = 200; + +endmodule diff --git a/tests/svinterfaces/svinterface1_ref.v b/tests/svinterfaces/svinterface1_ref.v new file mode 100644 index 000000000..b119f4037 --- /dev/null +++ b/tests/svinterfaces/svinterface1_ref.v @@ -0,0 +1,107 @@ + +module TopModule( + input logic clk, + input logic rst, + input logic [1:0] sig, + input logic flip, + output logic [15:0] passThrough, + output logic [21:0] outOther, + output logic [1:0] sig_out); + + + logic MyInterfaceInstance_setting; + logic [3:0] MyInterfaceInstance_other_setting; + logic [1:0] MyInterfaceInstance_mysig_out; + + SubModule1 u_SubModule1 ( + .clk(clk), + .rst(rst), + .u_MyInterface_setting(MyInterfaceInstance_setting), + .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out), + .u_MyInterface_other_setting(MyInterfaceInstance_other_setting), + .outOther(outOther), + .passThrough (passThrough), + .sig (sig) + ); + + assign sig_out = MyInterfaceInstance_mysig_out; + + + assign MyInterfaceInstance_setting = flip; + +endmodule + + +module SubModule1( + input logic clk, + input logic rst, + input logic u_MyInterface_setting, + output logic [3:0] u_MyInterface_other_setting, + output logic [1:0] u_MyInterface_mysig_out, + output logic [21:0] outOther, + input logic [1:0] sig, + output logic [15:0] passThrough + ); + + always @(posedge clk or posedge rst) + if(rst) + u_MyInterface_mysig_out <= 0; + else begin + if(u_MyInterface_setting) + u_MyInterface_mysig_out <= sig; + else + u_MyInterface_mysig_out <= ~sig; + end + + logic MyInterfaceInstanceInSub_setting; + logic [21:0] MyInterfaceInstanceInSub_other_setting; + logic [1:0] MyInterfaceInstanceInSub_mysig_out; + + + SubModule2 u_SubModule2 ( + .clk(clk), + .rst(rst), + .u_MyInterfaceInSub2_setting(u_MyInterface_setting), + .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out), + .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting), + .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting), + .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out), + .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting), + .passThrough (passThrough) + ); + assign outOther = MyInterfaceInstanceInSub_other_setting; + + assign MyInterfaceInstanceInSub_setting = 0; + assign MyInterfaceInstanceInSub_mysig_out = sig; + +endmodule + +module SubModule2( + + input logic clk, + input logic rst, + input logic u_MyInterfaceInSub2_setting, + output logic [3:0] u_MyInterfaceInSub2_other_setting, + input logic [1:0] u_MyInterfaceInSub2_mysig_out, + input logic u_MyInterfaceInSub3_setting, + output logic [21:0] u_MyInterfaceInSub3_other_setting, + input logic [1:0] u_MyInterfaceInSub3_mysig_out, + output logic [15:0] passThrough + + ); + + always @(u_MyInterfaceInSub3_mysig_out) begin + if (u_MyInterfaceInSub3_mysig_out == 2'b00) + u_MyInterfaceInSub3_other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b01) + u_MyInterfaceInSub3_other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b10) + u_MyInterfaceInSub3_other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3_other_setting[21:0] = 4000; + end + + assign passThrough[7:0] = 124; + assign passThrough[15:8] = 200; + +endmodule diff --git a/tests/svinterfaces/svinterface1_tb.v b/tests/svinterfaces/svinterface1_tb.v new file mode 100644 index 000000000..44c3b5f68 --- /dev/null +++ b/tests/svinterfaces/svinterface1_tb.v @@ -0,0 +1,57 @@ +`timescale 1ns/10ps + +module svinterface1_tb; + + + logic clk; + logic rst; + logic [21:0] outOther; + logic [1:0] sig; + logic [1:0] sig_out; + logic flip; + logic [15:0] passThrough; + integer outfile; + + TopModule u_dut ( + .clk(clk), + .rst(rst), + .outOther(outOther), + .sig(sig), + .flip(flip), + .passThrough(passThrough), + .sig_out(sig_out) + ); + + initial begin + clk = 0; + while(1) begin + clk = ~clk; + #50; + end + end + + initial begin + outfile = $fopen("output.txt"); + rst = 1; + sig = 0; + flip = 0; + @(posedge clk); + #(2); + rst = 0; + @(posedge clk); + for(int j=0;j<2;j++) begin + for(int i=0;i<20;i++) begin + #(2); + flip = j; + sig = i; + @(posedge clk); + end + end + $finish; + end + + always @(negedge clk) begin + $fdisplay(outfile, "%d %d %d", outOther, sig_out, passThrough); + end + +endmodule diff --git a/tests/svinterfaces/svinterface_at_top.sv b/tests/svinterfaces/svinterface_at_top.sv new file mode 100644 index 000000000..b5aa8c8f5 --- /dev/null +++ b/tests/svinterfaces/svinterface_at_top.sv @@ -0,0 +1,125 @@ + + +module TopModule( + input logic clk, + input logic rst, + output logic [21:0] outOther, + input logic [1:0] sig, + input logic flip, + output logic [1:0] sig_out, + MyInterface.submodule1 interfaceInstanceAtTop, + output logic [15:0] passThrough); + + MyInterface #(.WIDTH(4)) MyInterfaceInstance(); + + SubModule1 u_SubModule1 ( + .clk(clk), + .rst(rst), + .u_MyInterface(MyInterfaceInstance), + .u_MyInterfaceFromTop(interfaceInstanceAtTop), + .outOther(outOther), + .sig (sig) + ); + + assign sig_out = MyInterfaceInstance.mysig_out; + + + assign MyInterfaceInstance.setting = flip; + + assign passThrough = MyInterfaceInstance.passThrough; + +endmodule + +interface MyInterface #( + parameter WIDTH = 3)( + ); + + logic setting; + logic [WIDTH-1:0] other_setting; + + logic [1:0] mysig_out; + + logic [15:0] passThrough; + + modport submodule1 ( + input setting, + output other_setting, + output mysig_out, + output passThrough + ); + + modport submodule2 ( + input setting, + output other_setting, + input mysig_out, + output passThrough + ); + +endinterface + + +module SubModule1( + input logic clk, + input logic rst, + MyInterface.submodule1 u_MyInterface, + MyInterface.submodule1 u_MyInterfaceFromTop, + input logic [1:0] sig, + output logic [21:0] outOther + + ); + + + always_ff @(posedge clk or posedge rst) + if(rst) + u_MyInterface.mysig_out <= 0; + else begin + if(u_MyInterface.setting) + u_MyInterface.mysig_out <= sig; + else + u_MyInterface.mysig_out <= ~sig; + end + + MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub(); + + SubModule2 u_SubModule2 ( + .clk(clk), + .rst(rst), + .u_MyInterfaceFromTopDown(u_MyInterfaceFromTop), + .u_MyInterfaceInSub2(u_MyInterface), + .u_MyInterfaceInSub3(MyInterfaceInstanceInSub) + ); + + assign outOther = MyInterfaceInstanceInSub.other_setting; + + assign MyInterfaceInstanceInSub.setting = 0; + assign MyInterfaceInstanceInSub.mysig_out = sig; + +endmodule + +module SubModule2( + + input logic clk, + input logic rst, + MyInterface.submodule2 u_MyInterfaceInSub2, + MyInterface.submodule1 u_MyInterfaceFromTopDown, + MyInterface.submodule2 u_MyInterfaceInSub3 + + ); + + assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 : 20; + + always_comb begin + if (u_MyInterfaceInSub3.mysig_out == 2'b00) + u_MyInterfaceInSub3.other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b01) + u_MyInterfaceInSub3.other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b10) + u_MyInterfaceInSub3.other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3.other_setting[21:0] = 4000; + end + + assign u_MyInterfaceInSub2.passThrough[7:0] = 124; + assign u_MyInterfaceInSub2.passThrough[15:8] = 200; + +endmodule diff --git a/tests/svinterfaces/svinterface_at_top_ref.v b/tests/svinterfaces/svinterface_at_top_ref.v new file mode 100644 index 000000000..7b54a26d6 --- /dev/null +++ b/tests/svinterfaces/svinterface_at_top_ref.v @@ -0,0 +1,120 @@ + +module TopModule( + input logic clk, + input logic rst, + input logic [1:0] sig, + input logic flip, + output logic [15:0] passThrough, + output logic [21:0] outOther, + input logic interfaceInstanceAtTop_setting, + output logic [2:0] interfaceInstanceAtTop_other_setting, + output logic [1:0] interfaceInstanceAtTop_mysig_out, + output logic [15:0] interfaceInstanceAtTop_passThrough, + output logic [1:0] sig_out); + + + logic MyInterfaceInstance_setting; + logic [3:0] MyInterfaceInstance_other_setting; + logic [1:0] MyInterfaceInstance_mysig_out; + + SubModule1 u_SubModule1 ( + .clk(clk), + .rst(rst), + .u_MyInterface_setting(MyInterfaceInstance_setting), + .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out), + .u_MyInterface_other_setting(MyInterfaceInstance_other_setting), + .u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting), + .u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting), + .u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out), + .u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough), + .outOther(outOther), + .passThrough (passThrough), + .sig (sig) + ); + + assign sig_out = MyInterfaceInstance_mysig_out; + + + assign MyInterfaceInstance_setting = flip; + +endmodule + + +module SubModule1( + input logic clk, + input logic rst, + input logic u_MyInterface_setting, + output logic [3:0] u_MyInterface_other_setting, + output logic [1:0] u_MyInterface_mysig_out, + output logic [21:0] outOther, + input logic [1:0] sig, + input logic u_MyInterfaceFromTop_setting, + output logic [2:0] u_MyInterfaceFromTop_other_setting, + output logic [1:0] u_MyInterfaceFromTop_mysig_out, + output logic [14:0] u_MyInterfaceFromTop_passThrough, + output logic [15:0] passThrough + ); + + always @(posedge clk or posedge rst) + if(rst) + u_MyInterface_mysig_out <= 0; + else begin + if(u_MyInterface_setting) + u_MyInterface_mysig_out <= sig; + else + u_MyInterface_mysig_out <= ~sig; + end + + logic MyInterfaceInstanceInSub_setting; + logic [21:0] MyInterfaceInstanceInSub_other_setting; + logic [1:0] MyInterfaceInstanceInSub_mysig_out; + + assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20; + + SubModule2 u_SubModule2 ( + .clk(clk), + .rst(rst), + .u_MyInterfaceInSub2_setting(u_MyInterface_setting), + .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out), + .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting), + .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting), + .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out), + .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting), + .passThrough (passThrough) + ); + assign outOther = MyInterfaceInstanceInSub_other_setting; + + assign MyInterfaceInstanceInSub_setting = 0; + assign MyInterfaceInstanceInSub_mysig_out = sig; + +endmodule + +module SubModule2( + + input logic clk, + input logic rst, + input logic u_MyInterfaceInSub2_setting, + output logic [3:0] u_MyInterfaceInSub2_other_setting, + input logic [1:0] u_MyInterfaceInSub2_mysig_out, + input logic u_MyInterfaceInSub3_setting, + output logic [21:0] u_MyInterfaceInSub3_other_setting, + input logic [1:0] u_MyInterfaceInSub3_mysig_out, + output logic [15:0] passThrough + + ); + + always @(u_MyInterfaceInSub3_mysig_out) begin + if (u_MyInterfaceInSub3_mysig_out == 2'b00) + u_MyInterfaceInSub3_other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b01) + u_MyInterfaceInSub3_other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b10) + u_MyInterfaceInSub3_other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3_other_setting[21:0] = 4000; + end + + assign passThrough[7:0] = 124; + assign passThrough[15:8] = 200; + +endmodule diff --git a/tests/svinterfaces/svinterface_at_top_tb.v b/tests/svinterfaces/svinterface_at_top_tb.v new file mode 100644 index 000000000..bf37a148d --- /dev/null +++ b/tests/svinterfaces/svinterface_at_top_tb.v @@ -0,0 +1,68 @@ +`timescale 1ns/10ps + +module svinterface_at_top_tb; + + + logic clk; + logic rst; + logic [21:0] outOther; + logic [1:0] sig; + logic [1:0] sig_out; + logic flip; + logic [15:0] passThrough; + integer outfile; + + logic interfaceInstanceAtTop_setting; + logic [2:0] interfaceInstanceAtTop_other_setting; + logic [1:0] interfaceInstanceAtTop_mysig_out; + logic [15:0] interfaceInstanceAtTop_passThrough; + + + TopModule u_dut ( + .clk(clk), + .rst(rst), + .outOther(outOther), + .sig(sig), + .flip(flip), + .passThrough(passThrough), + .interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting), + .interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting), + .interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out), + .interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough), + .sig_out(sig_out) + ); + + initial begin + clk = 0; + while(1) begin + clk = ~clk; + #50; + end + end + + initial begin + outfile = $fopen("output.txt"); + rst = 1; + interfaceInstanceAtTop_setting = 0; + sig = 0; + flip = 0; + @(posedge clk); + #(2); + rst = 0; + @(posedge clk); + for(int j=0;j<2;j++) begin + for(int i=0;i<20;i++) begin + #(2); + flip = j; + sig = i; + @(posedge clk); + end + end + $finish; + end + + always @(negedge clk) begin + $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out); + end + +endmodule diff --git a/tests/svinterfaces/svinterface_at_top_tb_wrapper.v b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v new file mode 100644 index 000000000..b344a7b88 --- /dev/null +++ b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v @@ -0,0 +1,68 @@ +`timescale 1ns/10ps + +module svinterface_at_top_tb_wrapper; + + + logic clk; + logic rst; + logic [21:0] outOther; + logic [1:0] sig; + logic [1:0] sig_out; + logic flip; + logic [15:0] passThrough; + integer outfile; + + logic interfaceInstanceAtTop_setting; + logic [2:0] interfaceInstanceAtTop_other_setting; + logic [1:0] interfaceInstanceAtTop_mysig_out; + logic [15:0] interfaceInstanceAtTop_passThrough; + + + TopModule u_dut ( + .clk(clk), + .rst(rst), + .outOther(outOther), + .sig(sig), + .flip(flip), + .passThrough(passThrough), + .\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting), + .\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting), + .\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out), + .\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough), + .sig_out(sig_out) + ); + + initial begin + clk = 0; + while(1) begin + clk = ~clk; + #50; + end + end + + initial begin + outfile = $fopen("output.txt"); + rst = 1; + sig = 0; + interfaceInstanceAtTop_setting = 0; + flip = 0; + @(posedge clk); + #(2); + rst = 0; + @(posedge clk); + for(int j=0;j<2;j++) begin + for(int i=0;i<20;i++) begin + #(2); + flip = j; + sig = i; + @(posedge clk); + end + end + $finish; + end + + always @(negedge clk) begin + $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out); + end + +endmodule diff --git a/tests/svinterfaces/svinterface_at_top_wrapper.v b/tests/svinterfaces/svinterface_at_top_wrapper.v new file mode 100644 index 000000000..64f906c07 --- /dev/null +++ b/tests/svinterfaces/svinterface_at_top_wrapper.v @@ -0,0 +1,33 @@ +`timescale 1ns/10ps + +module svinterface_at_top_wrapper( + input logic clk, + input logic rst, + output logic [21:0] outOther, + input logic [1:0] sig, + output logic [1:0] sig_out, + input logic flip, + output logic [15:0] passThrough, + + input logic interfaceInstanceAtTop_setting, + output logic [2:0] interfaceInstanceAtTop_other_setting, + output logic [1:0] interfaceInstanceAtTop_mysig_out, + output logic [15:0] interfaceInstanceAtTop_passThrough, + ); + + + TopModule u_dut ( + .clk(clk), + .rst(rst), + .outOther(outOther), + .sig(sig), + .flip(flip), + .passThrough(passThrough), + .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting), + .\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting), + .\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out), + .\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough), + .sig_out(sig_out) + ); + +endmodule |