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-rwxr-xr-xtests/svinterfaces/run-test.sh1
-rwxr-xr-xtests/svinterfaces/runone.sh7
-rw-r--r--tests/svinterfaces/svinterface_at_top.sv125
-rw-r--r--tests/svinterfaces/svinterface_at_top_ref.v120
-rw-r--r--tests/svinterfaces/svinterface_at_top_tb.v68
-rw-r--r--tests/svinterfaces/svinterface_at_top_tb_wrapper.v68
-rw-r--r--tests/svinterfaces/svinterface_at_top_wrapper.v33
7 files changed, 420 insertions, 2 deletions
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
index 1630859bd..86567d1c1 100755
--- a/tests/svinterfaces/run-test.sh
+++ b/tests/svinterfaces/run-test.sh
@@ -3,3 +3,4 @@
./runone.sh svinterface1
+./runone.sh svinterface_at_top
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 345801389..0adecc797 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -22,11 +22,14 @@ iverilog -g2012 ${TESTNAME}_syn.v
iverilog -g2012 ${TESTNAME}_ref_syn.v
set +e
-
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
./a.out
mv output.txt reference_result.txt
-iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+if [ -f ${TESTNAME}_wrapper.v ] ; then
+ iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v
+else
+ iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+fi
./a.out
mv output.txt dut_result.txt
diff --git a/tests/svinterfaces/svinterface_at_top.sv b/tests/svinterfaces/svinterface_at_top.sv
new file mode 100644
index 000000000..b5aa8c8f5
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top.sv
@@ -0,0 +1,125 @@
+
+
+module TopModule(
+ input logic clk,
+ input logic rst,
+ output logic [21:0] outOther,
+ input logic [1:0] sig,
+ input logic flip,
+ output logic [1:0] sig_out,
+ MyInterface.submodule1 interfaceInstanceAtTop,
+ output logic [15:0] passThrough);
+
+ MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+ SubModule1 u_SubModule1 (
+ .clk(clk),
+ .rst(rst),
+ .u_MyInterface(MyInterfaceInstance),
+ .u_MyInterfaceFromTop(interfaceInstanceAtTop),
+ .outOther(outOther),
+ .sig (sig)
+ );
+
+ assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+ assign MyInterfaceInstance.setting = flip;
+
+ assign passThrough = MyInterfaceInstance.passThrough;
+
+endmodule
+
+interface MyInterface #(
+ parameter WIDTH = 3)(
+ );
+
+ logic setting;
+ logic [WIDTH-1:0] other_setting;
+
+ logic [1:0] mysig_out;
+
+ logic [15:0] passThrough;
+
+ modport submodule1 (
+ input setting,
+ output other_setting,
+ output mysig_out,
+ output passThrough
+ );
+
+ modport submodule2 (
+ input setting,
+ output other_setting,
+ input mysig_out,
+ output passThrough
+ );
+
+endinterface
+
+
+module SubModule1(
+ input logic clk,
+ input logic rst,
+ MyInterface.submodule1 u_MyInterface,
+ MyInterface.submodule1 u_MyInterfaceFromTop,
+ input logic [1:0] sig,
+ output logic [21:0] outOther
+
+ );
+
+
+ always_ff @(posedge clk or posedge rst)
+ if(rst)
+ u_MyInterface.mysig_out <= 0;
+ else begin
+ if(u_MyInterface.setting)
+ u_MyInterface.mysig_out <= sig;
+ else
+ u_MyInterface.mysig_out <= ~sig;
+ end
+
+ MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+ SubModule2 u_SubModule2 (
+ .clk(clk),
+ .rst(rst),
+ .u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
+ .u_MyInterfaceInSub2(u_MyInterface),
+ .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
+ );
+
+ assign outOther = MyInterfaceInstanceInSub.other_setting;
+
+ assign MyInterfaceInstanceInSub.setting = 0;
+ assign MyInterfaceInstanceInSub.mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+ input logic clk,
+ input logic rst,
+ MyInterface.submodule2 u_MyInterfaceInSub2,
+ MyInterface.submodule1 u_MyInterfaceFromTopDown,
+ MyInterface.submodule2 u_MyInterfaceInSub3
+
+ );
+
+ assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 : 20;
+
+ always_comb begin
+ if (u_MyInterfaceInSub3.mysig_out == 2'b00)
+ u_MyInterfaceInSub3.other_setting[21:0] = 1000;
+ else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
+ u_MyInterfaceInSub3.other_setting[21:0] = 2000;
+ else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
+ u_MyInterfaceInSub3.other_setting[21:0] = 3000;
+ else
+ u_MyInterfaceInSub3.other_setting[21:0] = 4000;
+ end
+
+ assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
+ assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_ref.v b/tests/svinterfaces/svinterface_at_top_ref.v
new file mode 100644
index 000000000..7b54a26d6
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_ref.v
@@ -0,0 +1,120 @@
+
+module TopModule(
+ input logic clk,
+ input logic rst,
+ input logic [1:0] sig,
+ input logic flip,
+ output logic [15:0] passThrough,
+ output logic [21:0] outOther,
+ input logic interfaceInstanceAtTop_setting,
+ output logic [2:0] interfaceInstanceAtTop_other_setting,
+ output logic [1:0] interfaceInstanceAtTop_mysig_out,
+ output logic [15:0] interfaceInstanceAtTop_passThrough,
+ output logic [1:0] sig_out);
+
+
+ logic MyInterfaceInstance_setting;
+ logic [3:0] MyInterfaceInstance_other_setting;
+ logic [1:0] MyInterfaceInstance_mysig_out;
+
+ SubModule1 u_SubModule1 (
+ .clk(clk),
+ .rst(rst),
+ .u_MyInterface_setting(MyInterfaceInstance_setting),
+ .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
+ .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
+ .u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
+ .u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
+ .u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+ .u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
+ .outOther(outOther),
+ .passThrough (passThrough),
+ .sig (sig)
+ );
+
+ assign sig_out = MyInterfaceInstance_mysig_out;
+
+
+ assign MyInterfaceInstance_setting = flip;
+
+endmodule
+
+
+module SubModule1(
+ input logic clk,
+ input logic rst,
+ input logic u_MyInterface_setting,
+ output logic [3:0] u_MyInterface_other_setting,
+ output logic [1:0] u_MyInterface_mysig_out,
+ output logic [21:0] outOther,
+ input logic [1:0] sig,
+ input logic u_MyInterfaceFromTop_setting,
+ output logic [2:0] u_MyInterfaceFromTop_other_setting,
+ output logic [1:0] u_MyInterfaceFromTop_mysig_out,
+ output logic [14:0] u_MyInterfaceFromTop_passThrough,
+ output logic [15:0] passThrough
+ );
+
+ always @(posedge clk or posedge rst)
+ if(rst)
+ u_MyInterface_mysig_out <= 0;
+ else begin
+ if(u_MyInterface_setting)
+ u_MyInterface_mysig_out <= sig;
+ else
+ u_MyInterface_mysig_out <= ~sig;
+ end
+
+ logic MyInterfaceInstanceInSub_setting;
+ logic [21:0] MyInterfaceInstanceInSub_other_setting;
+ logic [1:0] MyInterfaceInstanceInSub_mysig_out;
+
+ assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20;
+
+ SubModule2 u_SubModule2 (
+ .clk(clk),
+ .rst(rst),
+ .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
+ .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
+ .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
+ .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
+ .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
+ .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
+ .passThrough (passThrough)
+ );
+ assign outOther = MyInterfaceInstanceInSub_other_setting;
+
+ assign MyInterfaceInstanceInSub_setting = 0;
+ assign MyInterfaceInstanceInSub_mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+ input logic clk,
+ input logic rst,
+ input logic u_MyInterfaceInSub2_setting,
+ output logic [3:0] u_MyInterfaceInSub2_other_setting,
+ input logic [1:0] u_MyInterfaceInSub2_mysig_out,
+ input logic u_MyInterfaceInSub3_setting,
+ output logic [21:0] u_MyInterfaceInSub3_other_setting,
+ input logic [1:0] u_MyInterfaceInSub3_mysig_out,
+ output logic [15:0] passThrough
+
+ );
+
+ always @(u_MyInterfaceInSub3_mysig_out) begin
+ if (u_MyInterfaceInSub3_mysig_out == 2'b00)
+ u_MyInterfaceInSub3_other_setting[21:0] = 1000;
+ else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
+ u_MyInterfaceInSub3_other_setting[21:0] = 2000;
+ else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
+ u_MyInterfaceInSub3_other_setting[21:0] = 3000;
+ else
+ u_MyInterfaceInSub3_other_setting[21:0] = 4000;
+ end
+
+ assign passThrough[7:0] = 124;
+ assign passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb.v b/tests/svinterfaces/svinterface_at_top_tb.v
new file mode 100644
index 000000000..bf37a148d
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb;
+
+
+ logic clk;
+ logic rst;
+ logic [21:0] outOther;
+ logic [1:0] sig;
+ logic [1:0] sig_out;
+ logic flip;
+ logic [15:0] passThrough;
+ integer outfile;
+
+ logic interfaceInstanceAtTop_setting;
+ logic [2:0] interfaceInstanceAtTop_other_setting;
+ logic [1:0] interfaceInstanceAtTop_mysig_out;
+ logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+ TopModule u_dut (
+ .clk(clk),
+ .rst(rst),
+ .outOther(outOther),
+ .sig(sig),
+ .flip(flip),
+ .passThrough(passThrough),
+ .interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting),
+ .interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting),
+ .interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+ .interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough),
+ .sig_out(sig_out)
+ );
+
+ initial begin
+ clk = 0;
+ while(1) begin
+ clk = ~clk;
+ #50;
+ end
+ end
+
+ initial begin
+ outfile = $fopen("output.txt");
+ rst = 1;
+ interfaceInstanceAtTop_setting = 0;
+ sig = 0;
+ flip = 0;
+ @(posedge clk);
+ #(2);
+ rst = 0;
+ @(posedge clk);
+ for(int j=0;j<2;j++) begin
+ for(int i=0;i<20;i++) begin
+ #(2);
+ flip = j;
+ sig = i;
+ @(posedge clk);
+ end
+ end
+ $finish;
+ end
+
+ always @(negedge clk) begin
+ $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+ end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb_wrapper.v b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
new file mode 100644
index 000000000..b344a7b88
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb_wrapper;
+
+
+ logic clk;
+ logic rst;
+ logic [21:0] outOther;
+ logic [1:0] sig;
+ logic [1:0] sig_out;
+ logic flip;
+ logic [15:0] passThrough;
+ integer outfile;
+
+ logic interfaceInstanceAtTop_setting;
+ logic [2:0] interfaceInstanceAtTop_other_setting;
+ logic [1:0] interfaceInstanceAtTop_mysig_out;
+ logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+ TopModule u_dut (
+ .clk(clk),
+ .rst(rst),
+ .outOther(outOther),
+ .sig(sig),
+ .flip(flip),
+ .passThrough(passThrough),
+ .\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting),
+ .\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting),
+ .\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out),
+ .\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough),
+ .sig_out(sig_out)
+ );
+
+ initial begin
+ clk = 0;
+ while(1) begin
+ clk = ~clk;
+ #50;
+ end
+ end
+
+ initial begin
+ outfile = $fopen("output.txt");
+ rst = 1;
+ sig = 0;
+ interfaceInstanceAtTop_setting = 0;
+ flip = 0;
+ @(posedge clk);
+ #(2);
+ rst = 0;
+ @(posedge clk);
+ for(int j=0;j<2;j++) begin
+ for(int i=0;i<20;i++) begin
+ #(2);
+ flip = j;
+ sig = i;
+ @(posedge clk);
+ end
+ end
+ $finish;
+ end
+
+ always @(negedge clk) begin
+ $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+ end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_wrapper.v b/tests/svinterfaces/svinterface_at_top_wrapper.v
new file mode 100644
index 000000000..64f906c07
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_wrapper.v
@@ -0,0 +1,33 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_wrapper(
+ input logic clk,
+ input logic rst,
+ output logic [21:0] outOther,
+ input logic [1:0] sig,
+ output logic [1:0] sig_out,
+ input logic flip,
+ output logic [15:0] passThrough,
+
+ input logic interfaceInstanceAtTop_setting,
+ output logic [2:0] interfaceInstanceAtTop_other_setting,
+ output logic [1:0] interfaceInstanceAtTop_mysig_out,
+ output logic [15:0] interfaceInstanceAtTop_passThrough,
+ );
+
+
+ TopModule u_dut (
+ .clk(clk),
+ .rst(rst),
+ .outOther(outOther),
+ .sig(sig),
+ .flip(flip),
+ .passThrough(passThrough),
+ .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
+ .\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
+ .\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
+ .\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
+ .sig_out(sig_out)
+ );
+
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 01:04:41 +0000