14 files changed, 232 insertions, 0 deletions
diff --git a/tests/arch/machxo2/.gitignore b/tests/arch/machxo2/.gitignore
new file mode 100644
index 000000000..1d329c933
--- /dev/null
+++ b/tests/arch/machxo2/.gitignore
@@ -0,0 +1,2 @@
+*.log
+/run-test.mk
diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys
new file mode 100644
index 000000000..d9497b818
--- /dev/null
+++ b/tests/arch/machxo2/add_sub.ys
@@ -0,0 +1,8 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:LUT4
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys
new file mode 100644
index 000000000..83a79a9d6
--- /dev/null
+++ b/tests/arch/machxo2/dffs.ys
@@ -0,0 +1,19 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:FACADE_FF
+select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 2 t:FACADE_FF t:LUT4
+select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys
new file mode 100644
index 000000000..847a61161
--- /dev/null
+++ b/tests/arch/machxo2/fsm.ys
@@ -0,0 +1,15 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-max 16 t:LUT4
+select -assert-count 6 t:FACADE_FF
+select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys
new file mode 100644
index 000000000..bf93ab128
--- /dev/null
+++ b/tests/arch/machxo2/logic.ys
@@ -0,0 +1,8 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 9 t:LUT4
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
new file mode 100644
index 000000000..6c8aa857c
--- /dev/null
+++ b/tests/arch/machxo2/mux.ys
@@ -0,0 +1,40 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT4
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:LUT4
+
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT4
+
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 11 t:LUT4
+
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/run-test.sh b/tests/arch/machxo2/run-test.sh
new file mode 100644
index 000000000..4be4b70ae
--- /dev/null
+++ b/tests/arch/machxo2/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys
new file mode 100644
index 000000000..87fdab0fa
--- /dev/null
+++ b/tests/arch/machxo2/shifter.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:FACADE_FF
+select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys
new file mode 100644
index 000000000..9c00a8bcf
--- /dev/null
+++ b/tests/arch/machxo2/tribuf.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+flatten
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 3 t:FACADE_IO
+select -assert-count 1 t:$not
+select -assert-none t:FACADE_IO t:$not %% t:* %D
diff --git a/tests/sat/bug2595.ys b/tests/sat/bug2595.ys
new file mode 100644
index 000000000..f668fd747
--- /dev/null
+++ b/tests/sat/bug2595.ys
@@ -0,0 +1,18 @@
+read_ilang <<EOT
+module \top
+  wire input 3 \A
+  wire width 2 input 2 \B
+  wire width 2 input 1 \S
+  wire \Y
+  cell $pmux \my_pmux
+    parameter signed \S_WIDTH 2
+    parameter signed \WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \S \S
+    connect \Y \Y
+  end
+end
+EOT
+
+assertpmux
diff --git a/tests/various/fib_tern.v b/tests/various/fib_tern.v
new file mode 100644
index 000000000..fefde74ce
--- /dev/null
+++ b/tests/various/fib_tern.v
@@ -0,0 +1,70 @@
+module gate(
+    off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+    input wire signed [31:0] off;
+
+    function automatic blah(
+        input x
+    );
+        blah = x;
+    endfunction
+
+    function automatic integer fib(
+        input integer k
+    );
+        fib = k == 0
+                ? 0
+                : k == 1
+                    ? 1
+                    : fib(k - 1) + fib(k - 2);
+    endfunction
+
+    function automatic integer fib_wrap(
+        input integer k,
+        output integer o
+    );
+        o = off + fib(k);
+    endfunction
+
+    output integer fib0;
+    output integer fib1;
+    output integer fib2;
+    output integer fib3;
+    output integer fib4;
+    output integer fib5;
+    output integer fib6;
+    output integer fib7;
+    output integer fib8;
+    output integer fib9;
+
+    initial begin : blk
+        integer unused;
+        unused = fib_wrap(0, fib0);
+        unused = fib_wrap(1, fib1);
+        unused = fib_wrap(2, fib2);
+        unused = fib_wrap(3, fib3);
+        unused = fib_wrap(4, fib4);
+        unused = fib_wrap(5, fib5);
+        unused = fib_wrap(6, fib6);
+        unused = fib_wrap(7, fib7);
+        unused = fib_wrap(8, fib8);
+        unused = fib_wrap(9, fib9);
+    end
+endmodule
+
+module gold(
+    off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+    input wire signed [31:0] off;
+
+    output integer fib0 = off + 0;
+    output integer fib1 = off + 1;
+    output integer fib2 = off + 1;
+    output integer fib3 = off + 2;
+    output integer fib4 = off + 3;
+    output integer fib5 = off + 5;
+    output integer fib6 = off + 8;
+    output integer fib7 = off + 13;
+    output integer fib8 = off + 21;
+    output integer fib9 = off + 34;
+endmodule
diff --git a/tests/various/fib_tern.ys b/tests/various/fib_tern.ys
new file mode 100644
index 000000000..e5bf186e1
--- /dev/null
+++ b/tests/various/fib_tern.ys
@@ -0,0 +1,6 @@
+read_verilog fib_tern.v
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/verilog/macro_unapplied.ys b/tests/verilog/macro_unapplied.ys
new file mode 100644
index 000000000..81eb10b8b
--- /dev/null
+++ b/tests/verilog/macro_unapplied.ys
@@ -0,0 +1,17 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOT
+`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
+module top;
+    `MACRO();
+endmodule
+EOT
+
+design -reset
+
+logger -expect error "Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
+read_verilog -sv <<EOT
+`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
+module top;
+    `MACRO;
+endmodule
+EOT
diff --git a/tests/verilog/macro_unapplied_newline.ys b/tests/verilog/macro_unapplied_newline.ys
new file mode 100644
index 000000000..a3f88d5b4
--- /dev/null
+++ b/tests/verilog/macro_unapplied_newline.ys
@@ -0,0 +1,5 @@
+logger -expect error "Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'" 1
+read_verilog -sv <<EOT
+`define foo(a=1) (a)
+`foo
+EOT