diff options
Diffstat (limited to 'tests')
50 files changed, 1254 insertions, 5 deletions
diff --git a/tests/sim/.gitignore b/tests/sim/.gitignore new file mode 100644 index 000000000..2c96b65f8 --- /dev/null +++ b/tests/sim/.gitignore @@ -0,0 +1,6 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench +*.out +*.fst diff --git a/tests/sim/adff.v b/tests/sim/adff.v new file mode 100644 index 000000000..8c8fb0acf --- /dev/null +++ b/tests/sim/adff.v @@ -0,0 +1,7 @@ +module adff( input d, clk, rst, output reg q ); + always @( posedge clk, posedge rst ) + if (rst) + q <= 0; + else + q <= d; +endmodule diff --git a/tests/sim/adffe.v b/tests/sim/adffe.v new file mode 100644 index 000000000..55c7d8d4e --- /dev/null +++ b/tests/sim/adffe.v @@ -0,0 +1,8 @@ +module adffe( input d, clk, rst, en, output reg q ); + always @( posedge clk, posedge rst ) + if (rst) + q <= 0; + else + if (en) + q <= d; +endmodule diff --git a/tests/sim/adlatch.v b/tests/sim/adlatch.v new file mode 100644 index 000000000..5e8f48e49 --- /dev/null +++ b/tests/sim/adlatch.v @@ -0,0 +1,8 @@ +module adlatch( input d, rst, en, output reg q ); + always @* begin + if (rst) + q = 0; + else if (en) + q = d; + end +endmodule diff --git a/tests/sim/aldff.v b/tests/sim/aldff.v new file mode 100644 index 000000000..eeb0f0673 --- /dev/null +++ b/tests/sim/aldff.v @@ -0,0 +1,7 @@ +module aldff( input [0:3] d, input [0:3] ad, input clk, aload, output reg [0:3] q ); + always @( posedge clk, posedge aload) + if (aload) + q <= ad; + else + q <= d; +endmodule diff --git a/tests/sim/aldffe.v b/tests/sim/aldffe.v new file mode 100644 index 000000000..79c65afc4 --- /dev/null +++ b/tests/sim/aldffe.v @@ -0,0 +1,8 @@ +module aldffe( input [0:3] d, input [0:3] ad, input clk, aload, en, output reg [0:3] q ); + always @( posedge clk, posedge aload) + if (aload) + q <= ad; + else + if (en) + q <= d; +endmodule diff --git a/tests/sim/dff.v b/tests/sim/dff.v new file mode 100644 index 000000000..ce792b59a --- /dev/null +++ b/tests/sim/dff.v @@ -0,0 +1,4 @@ +module dff( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule diff --git a/tests/sim/dffe.v b/tests/sim/dffe.v new file mode 100644 index 000000000..853fcf66a --- /dev/null +++ b/tests/sim/dffe.v @@ -0,0 +1,5 @@ +module dffe( input clk, en, d, output reg q ); + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/sim/dffsr.v b/tests/sim/dffsr.v new file mode 100644 index 000000000..2158708f1 --- /dev/null +++ b/tests/sim/dffsr.v @@ -0,0 +1,9 @@ +module dffsr( input clk, d, clr, set, output reg q ); + always @( posedge clk, posedge set, posedge clr) + if ( clr ) + q <= 0; + else if (set) + q <= 1; + else + q <= d; +endmodule diff --git a/tests/sim/dlatch.v b/tests/sim/dlatch.v new file mode 100644 index 000000000..315b43216 --- /dev/null +++ b/tests/sim/dlatch.v @@ -0,0 +1,6 @@ +module dlatch( input d, en, output reg q ); + always @* begin + if ( en ) + q = d; + end +endmodule diff --git a/tests/sim/dlatchsr.v b/tests/sim/dlatchsr.v new file mode 100644 index 000000000..1d13ac2ad --- /dev/null +++ b/tests/sim/dlatchsr.v @@ -0,0 +1,11 @@ +module dlatchsr( input d, set, clr, en, output reg q ); + always @* begin + if ( clr ) + q = 0; + else if (set) + q = 1; + else + if (en) + q = d; + end +endmodule diff --git a/tests/sim/run-test.sh b/tests/sim/run-test.sh new file mode 100755 index 000000000..d34d1f3c9 --- /dev/null +++ b/tests/sim/run-test.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +echo "Generate FST for sim models" +find tb/* -name tb*.v | while read name; do + test_name=$(basename -s .v $name) + echo "Test $test_name" + verilog_name=${test_name:3}.v + iverilog -o tb/$test_name.out $name $verilog_name + ./tb/$test_name.out -fst +done +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/sim/sdff.v b/tests/sim/sdff.v new file mode 100644 index 000000000..6b25516e1 --- /dev/null +++ b/tests/sim/sdff.v @@ -0,0 +1,7 @@ +module sdff( input d, clk, rst, output reg q ); + always @( posedge clk) + if (rst) + q <= 0; + else + q <= d; +endmodule diff --git a/tests/sim/sdffce.v b/tests/sim/sdffce.v new file mode 100644 index 000000000..7d27d5741 --- /dev/null +++ b/tests/sim/sdffce.v @@ -0,0 +1,8 @@ +module sdffce( input d, clk, rst, en, output reg q ); + always @( posedge clk) + if(en) + if (rst) + q <= 0; + else + q <= d; +endmodule diff --git a/tests/sim/sdffe.v b/tests/sim/sdffe.v new file mode 100644 index 000000000..0a96693e1 --- /dev/null +++ b/tests/sim/sdffe.v @@ -0,0 +1,8 @@ +module sdffe( input d, clk, rst, en, output reg q ); + always @( posedge clk) + if (rst) + q <= 0; + else + if (en) + q <= d; +endmodule diff --git a/tests/sim/sim_adff.ys b/tests/sim/sim_adff.ys new file mode 100644 index 000000000..6efd804a9 --- /dev/null +++ b/tests/sim/sim_adff.ys @@ -0,0 +1,6 @@ +read_verilog adff.v +proc +opt_dff +stat +select -assert-count 1 t:$adff +sim -clock clk -r tb_adff.fst -scope tb_adff.uut -sim-cmp adff diff --git a/tests/sim/sim_adffe.ys b/tests/sim/sim_adffe.ys new file mode 100644 index 000000000..47a51ebce --- /dev/null +++ b/tests/sim/sim_adffe.ys @@ -0,0 +1,6 @@ +read_verilog adffe.v +proc +opt_dff +stat +select -assert-count 1 t:$adffe +sim -clock clk -r tb_adffe.fst -scope tb_adffe.uut -sim-cmp adffe diff --git a/tests/sim/sim_adlatch.ys b/tests/sim/sim_adlatch.ys new file mode 100644 index 000000000..eece7dc0d --- /dev/null +++ b/tests/sim/sim_adlatch.ys @@ -0,0 +1,10 @@ +read_verilog -icells <<EOT +module adlatch(input d, rst, en, output reg q); +$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(1'b0), .WIDTH(1)) uut (.EN(en), .ARST(rst), .D(d), .Q(q)); +endmodule +EOT +proc +opt_dff +stat +select -assert-count 1 t:$adlatch +sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch diff --git a/tests/sim/sim_aldff.ys b/tests/sim/sim_aldff.ys new file mode 100644 index 000000000..9c8b3bdfc --- /dev/null +++ b/tests/sim/sim_aldff.ys @@ -0,0 +1,6 @@ +read_verilog aldff.v +proc +opt_dff +stat +select -assert-count 1 t:$aldff +sim -clock clk -r tb_aldff.fst -scope tb_aldff.uut -sim-cmp aldff diff --git a/tests/sim/sim_aldffe.ys b/tests/sim/sim_aldffe.ys new file mode 100644 index 000000000..b191cf877 --- /dev/null +++ b/tests/sim/sim_aldffe.ys @@ -0,0 +1,6 @@ +read_verilog aldffe.v +proc +opt_dff +stat +select -assert-count 1 t:$aldffe +sim -clock clk -r tb_aldffe.fst -scope tb_aldffe.uut -sim-cmp aldffe diff --git a/tests/sim/sim_dff.ys b/tests/sim/sim_dff.ys new file mode 100644 index 000000000..12f402443 --- /dev/null +++ b/tests/sim/sim_dff.ys @@ -0,0 +1,6 @@ +read_verilog dff.v +proc +opt_dff +stat +select -assert-count 1 t:$dff +sim -clock clk -r tb_dff.fst -scope tb_dff.uut -sim-cmp dff diff --git a/tests/sim/sim_dffe.ys b/tests/sim/sim_dffe.ys new file mode 100644 index 000000000..f9b9e4767 --- /dev/null +++ b/tests/sim/sim_dffe.ys @@ -0,0 +1,6 @@ +read_verilog dffe.v +proc +opt_dff +stat +select -assert-count 1 t:$dffe +sim -clock clk -r tb_dffe.fst -scope tb_dffe.uut -sim-cmp dffe diff --git a/tests/sim/sim_dffsr.ys b/tests/sim/sim_dffsr.ys new file mode 100644 index 000000000..e99ee860d --- /dev/null +++ b/tests/sim/sim_dffsr.ys @@ -0,0 +1,6 @@ +read_verilog dffsr.v +proc +opt_dff +stat +select -assert-count 1 t:$dffsr +sim -clock clk -r tb_dffsr.fst -scope tb_dffsr.uut -sim-cmp dffsr diff --git a/tests/sim/sim_dlatch.ys b/tests/sim/sim_dlatch.ys new file mode 100644 index 000000000..79e4601e3 --- /dev/null +++ b/tests/sim/sim_dlatch.ys @@ -0,0 +1,6 @@ +read_verilog dlatch.v +proc +opt_dff +stat +select -assert-count 1 t:$dlatch +sim -r tb_dlatch.fst -scope tb_dlatch.uut -sim-cmp dlatch diff --git a/tests/sim/sim_dlatchsr.ys b/tests/sim/sim_dlatchsr.ys new file mode 100644 index 000000000..c83051c8b --- /dev/null +++ b/tests/sim/sim_dlatchsr.ys @@ -0,0 +1,10 @@ +read_verilog -icells <<EOT +module dlatchsr(input d, set, clr, en, output reg q); +$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q)); +endmodule +EOT +proc +opt_dff +stat +select -assert-count 1 t:$dlatchsr +sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr diff --git a/tests/sim/sim_sdff.ys b/tests/sim/sim_sdff.ys new file mode 100644 index 000000000..a812c5d80 --- /dev/null +++ b/tests/sim/sim_sdff.ys @@ -0,0 +1,6 @@ +read_verilog sdff.v +proc +opt_dff +stat +select -assert-count 1 t:$sdff +sim -clock clk -r tb_sdff.fst -scope tb_sdff.uut -sim-cmp sdff diff --git a/tests/sim/sim_sdffce.ys b/tests/sim/sim_sdffce.ys new file mode 100644 index 000000000..b28acb83d --- /dev/null +++ b/tests/sim/sim_sdffce.ys @@ -0,0 +1,6 @@ +read_verilog sdffce.v +proc +opt_dff +stat +select -assert-count 1 t:$sdffce +sim -clock clk -r tb_sdffce.fst -scope tb_sdffce.uut -sim-cmp sdffce diff --git a/tests/sim/sim_sdffe.ys b/tests/sim/sim_sdffe.ys new file mode 100644 index 000000000..044f78eb3 --- /dev/null +++ b/tests/sim/sim_sdffe.ys @@ -0,0 +1,6 @@ +read_verilog sdffe.v +proc +opt_dff +stat +select -assert-count 1 t:$sdffe +sim -clock clk -r tb_sdffe.fst -scope tb_sdffe.uut -sim-cmp sdffe diff --git a/tests/sim/tb/tb_adff.v b/tests/sim/tb/tb_adff.v new file mode 100755 index 000000000..f1bc3547e --- /dev/null +++ b/tests/sim/tb/tb_adff.v @@ -0,0 +1,40 @@ +`timescale 1ns/1ns +module tb_adff(); + reg clk = 0; + reg rst = 0; + reg d = 0; + wire q; + + adff uut(.clk(clk),.d(d),.rst(rst),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_adff"); + $dumpvars(0,tb_adff); + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_adffe.v b/tests/sim/tb/tb_adffe.v new file mode 100755 index 000000000..bb23f963d --- /dev/null +++ b/tests/sim/tb/tb_adffe.v @@ -0,0 +1,58 @@ +`timescale 1ns/1ns +module tb_adffe(); + reg clk = 0; + reg rst = 0; + reg d = 0; + reg en = 0; + wire q; + + adffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_adffe"); + $dumpvars(0,tb_adffe); + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_adlatch.v b/tests/sim/tb/tb_adlatch.v new file mode 100755 index 000000000..59dd498d2 --- /dev/null +++ b/tests/sim/tb/tb_adlatch.v @@ -0,0 +1,70 @@ +`timescale 1ns/1ns +module tb_adlatch(); + reg clk = 0; + reg rst = 0; + reg en = 0; + reg d = 0; + wire q; + + adlatch uut(.d(d),.rst(rst),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_adlatch"); + $dumpvars(0,tb_adlatch); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_aldff.v b/tests/sim/tb/tb_aldff.v new file mode 100755 index 000000000..0591c8b3c --- /dev/null +++ b/tests/sim/tb/tb_aldff.v @@ -0,0 +1,73 @@ +`timescale 1ns/1ns +module tb_aldff(); + reg clk = 0; + reg aload = 0; + reg [0:3] d = 4'b0000; + reg [0:3] ad = 4'b1010; + wire [0:3] q; + + aldff uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_aldff"); + $dumpvars(0,tb_aldff); + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 1; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 0; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 1; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 0; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_aldffe.v b/tests/sim/tb/tb_aldffe.v new file mode 100755 index 000000000..c3cb57f4e --- /dev/null +++ b/tests/sim/tb/tb_aldffe.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns +module tb_aldffe(); + reg clk = 0; + reg aload = 0; + reg [0:3] d = 4'b0000; + reg [0:3] ad = 4'b1010; + reg en = 0; + wire [0:3] q; + + aldffe uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_aldffe"); + $dumpvars(0,tb_aldffe); + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 1; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 0; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + en = 1; + aload = 1; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + aload = 0; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + d = 4'b1100; + #10 + d = 4'b0011; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_dff.v b/tests/sim/tb/tb_dff.v new file mode 100755 index 000000000..aa41d1c6c --- /dev/null +++ b/tests/sim/tb/tb_dff.v @@ -0,0 +1,47 @@ +`timescale 1ns/1ns +module tb_dff(); + reg clk = 0; + reg d = 0; + wire q; + + dff uut(.clk(clk),.d(d),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_dff"); + $dumpvars(0,tb_dff); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_dffe.v b/tests/sim/tb/tb_dffe.v new file mode 100755 index 000000000..4e262b928 --- /dev/null +++ b/tests/sim/tb/tb_dffe.v @@ -0,0 +1,42 @@ +`timescale 1ns/1ns +module tb_dffe(); + reg clk = 0; + reg en = 0; + reg d = 0; + wire q; + + dffe uut(.clk(clk),.d(d),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_dffe"); + $dumpvars(0,tb_dffe); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_dffsr.v b/tests/sim/tb/tb_dffsr.v new file mode 100755 index 000000000..6ecb85d67 --- /dev/null +++ b/tests/sim/tb/tb_dffsr.v @@ -0,0 +1,69 @@ +`timescale 1ns/1ns +module tb_dffsr(); + reg clk = 0; + reg d = 0; + reg set = 0; + reg clr = 0; + wire q; + + dffsr uut(.d(d),.clk(clk),.set(set),.clr(clr),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_dffsr"); + $dumpvars(0,tb_dffsr); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_dlatch.v b/tests/sim/tb/tb_dlatch.v new file mode 100755 index 000000000..aea6cb0a3 --- /dev/null +++ b/tests/sim/tb/tb_dlatch.v @@ -0,0 +1,50 @@ +`timescale 1ns/1ns +module tb_dlatch(); + reg clk = 0; + reg en = 0; + reg d = 0; + wire q; + + dlatch uut(.d(d),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_dlatch"); + $dumpvars(0,tb_dlatch); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v new file mode 100755 index 000000000..0105d3288 --- /dev/null +++ b/tests/sim/tb/tb_dlatchsr.v @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +module tb_dlatchsr(); + reg d = 0; + reg set = 0; + reg clr = 0; + wire q; + + dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q)); + + initial + begin + $dumpfile("tb_dlatchsr"); + $dumpvars(0,tb_dlatchsr); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_sdff.v b/tests/sim/tb/tb_sdff.v new file mode 100755 index 000000000..f8e2a1c9d --- /dev/null +++ b/tests/sim/tb/tb_sdff.v @@ -0,0 +1,48 @@ +`timescale 1ns/1ns +module tb_sdff(); + reg clk = 0; + reg rst = 0; + reg d = 0; + wire q; + + sdff uut(.clk(clk),.d(d),.rst(rst),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_sdff"); + $dumpvars(0,tb_sdff); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_sdffce.v b/tests/sim/tb/tb_sdffce.v new file mode 100755 index 000000000..1c9952806 --- /dev/null +++ b/tests/sim/tb/tb_sdffce.v @@ -0,0 +1,79 @@ +`timescale 1ns/1ns +module tb_sdffce(); + reg clk = 0; + reg rst = 0; + reg d = 0; + reg en = 0; + wire q; + + sdffce uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_sdffce"); + $dumpvars(0,tb_sdffce); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/sim/tb/tb_sdffe.v b/tests/sim/tb/tb_sdffe.v new file mode 100755 index 000000000..36072f93d --- /dev/null +++ b/tests/sim/tb/tb_sdffe.v @@ -0,0 +1,70 @@ +`timescale 1ns/1ns +module tb_sdffe(); + reg clk = 0; + reg rst = 0; + reg d = 0; + reg en = 0; + wire q; + + sdffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_sdffe"); + $dumpvars(0,tb_sdffe); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + en = 1; + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys index 6d7a7c6ad..b8de67968 100644 --- a/tests/various/param_struct.ys +++ b/tests/various/param_struct.ys @@ -41,8 +41,7 @@ always_comb begin assert(j == 1'b1); assert(k == 1'b0); assert(l == 3'b111); -// TODO: support access to whole sub-structs and unions -// assert(m == 2'b10); + assert(m == 2'b10); assert(u == 5'b11001); end endmodule diff --git a/tests/various/struct_access.sv b/tests/various/struct_access.sv new file mode 100644 index 000000000..d41a7114f --- /dev/null +++ b/tests/various/struct_access.sv @@ -0,0 +1,43 @@ +module dut(); +typedef struct packed { + logic a; + logic b; +} sub_sub_struct_t; + +typedef struct packed { + sub_sub_struct_t c; +} sub_struct_t; + +typedef struct packed { + sub_struct_t d; + sub_struct_t e; +} struct_t; + +parameter struct_t P = 4'b1100; + +localparam sub_struct_t f = P.d; +localparam sub_struct_t g = P.e; +localparam sub_sub_struct_t h = f.c; +localparam logic i = P.d.c.a; +localparam logic j = P.d.c.b; +localparam x = P.e; +localparam y = x.c; +localparam z = y.a; +localparam q = P.d; +localparam n = q.c.a; + +always_comb begin + assert(P == 4'b1100); + assert(f == 2'b11); + assert(g == 2'b00); + assert(h == 2'b11); + assert(i == 1'b1); + assert(j == 1'b1); + assert(x == 2'b00); + assert(y == 2'b00); + assert(x.c == 2'b00); + assert(y.b == 1'b0); + assert(n == 1'b1); + assert(z == 1'b0); +end +endmodule diff --git a/tests/various/struct_access.ys b/tests/various/struct_access.ys new file mode 100644 index 000000000..2282edd92 --- /dev/null +++ b/tests/various/struct_access.ys @@ -0,0 +1,5 @@ +read_verilog -sv struct_access.sv +hierarchy +proc +opt +sat -verify -seq 1 -prove-asserts -show-all diff --git a/tests/verilog/delay_time_scale.ys b/tests/verilog/delay_time_scale.ys new file mode 100644 index 000000000..f45ba7b26 --- /dev/null +++ b/tests/verilog/delay_time_scale.ys @@ -0,0 +1,25 @@ +logger -expect-no-warnings +read_verilog -sv <<EOT +module top; +wand x; +`define TEST(time_scale) if (1) assign #time_scale x = 1; + +`TEST(1s) +`TEST(1ms) +`TEST(1us) +`TEST(1ns) +`TEST(1ps) +`TEST(1fs) + +`TEST((1s)) +`TEST(( 1s)) +`TEST((1s )) +`TEST(( 1s )) + +`TEST(1.0s) +`TEST(1.1s) +`TEST(1.0e-1s) +`TEST(1e-1s) + +endmodule +EOT diff --git a/tests/verilog/dynamic_range_lhs.sh b/tests/verilog/dynamic_range_lhs.sh new file mode 100755 index 000000000..618204aed --- /dev/null +++ b/tests/verilog/dynamic_range_lhs.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +run() { + alt=$1 + span=$2 + left=$3 + right=$4 + echo "a=$alt s=$span l=$left r=$right" + + ../../yosys -q \ + -DALT=$alt \ + -DSPAN=$span \ + -DLEFT=$left \ + -DRIGHT=$right \ + -p "read_verilog dynamic_range_lhs.v" \ + -p "proc" \ + -p "equiv_make gold gate equiv" \ + -p "equiv_simple" \ + -p "equiv_status -assert" +} + +trap 'echo "ERROR in dynamic_range_lhs.sh span=$span left=$left right=$right" >&2; exit 1' ERR + +for alt in `seq 0 1`; do +for span in `seq 1 4`; do +for left in `seq -4 4`; do +for right in `seq $(expr $left + -3) $(expr $left + 3)`; do + run $alt $span $left $right +done +done +done +done diff --git a/tests/verilog/dynamic_range_lhs.v b/tests/verilog/dynamic_range_lhs.v new file mode 100644 index 000000000..ae291374d --- /dev/null +++ b/tests/verilog/dynamic_range_lhs.v @@ -0,0 +1,76 @@ +module gate( + output reg [`LEFT:`RIGHT] out_u, out_s, + (* nowrshmsk = `ALT *) + input wire data, + input wire [1:0] sel1, sel2 +); +always @* begin + out_u = 0; + out_s = 0; + case (`SPAN) + 1: begin + out_u[sel1*sel2] = data; + out_s[$signed(sel1*sel2)] = data; + end + 2: begin + out_u[sel1*sel2+:2] = {data, data}; + out_s[$signed(sel1*sel2)+:2] = {data, data}; + end + 3: begin + out_u[sel1*sel2+:3] = {data, data, data}; + out_s[$signed(sel1*sel2)+:3] = {data, data, data}; + end + 4: begin + out_u[sel1*sel2+:4] = {data, data, data, data}; + out_s[$signed(sel1*sel2)+:4] = {data, data, data, data}; + end + endcase +end +endmodule + +module gold( + output reg [`LEFT:`RIGHT] out_u, out_s, + input wire data, + input wire [1:0] sel1, sel2 +); +task set; + input integer a, b; + localparam LOW = `LEFT > `RIGHT ? `RIGHT : `LEFT; + localparam HIGH = `LEFT > `RIGHT ? `LEFT : `RIGHT; + if (LOW <= a && a <= HIGH) + out_u[a] = data; + if (LOW <= b && b <= HIGH) + out_s[b] = data; +endtask +always @* begin + out_u = 0; + out_s = 0; + case (sel1*sel2) + 2'b00: set(0, 0); + 2'b01: set(1, 1); + 2'b10: set(2, -2); + 2'b11: set(3, -1); + endcase + if (`SPAN >= 2) + case (sel1*sel2) + 2'b00: set(1, 1); + 2'b01: set(2, 2); + 2'b10: set(3, -1); + 2'b11: set(4, 0); + endcase + if (`SPAN >= 3) + case (sel1*sel2) + 2'b00: set(2, 2); + 2'b01: set(3, 3); + 2'b10: set(4, 0); + 2'b11: set(5, 1); + endcase + if (`SPAN >= 4) + case (sel1*sel2) + 2'b00: set(3, 3); + 2'b01: set(4, 4); + 2'b10: set(5, 1); + 2'b11: set(6, 2); + endcase +end +endmodule diff --git a/tests/verilog/func_upto.sv b/tests/verilog/func_upto.sv new file mode 100644 index 000000000..547e5d325 --- /dev/null +++ b/tests/verilog/func_upto.sv @@ -0,0 +1,77 @@ +`default_nettype none + +module evil; + parameter HI = 3; + parameter LO = 0; + parameter SPAN = 1; + parameter [HI:LO] A_VAL = 4'b0110; + parameter [HI:LO] B_VAL = 4'b1100; + parameter [2:0] SWAPS = 0; + + localparam D_LEFT = !(SWAPS[0]) ? HI : LO; + localparam D_RIGHT = (SWAPS[0]) ? HI : LO; + localparam E_LEFT = !(SWAPS[1]) ? HI : LO; + localparam E_RIGHT = (SWAPS[1]) ? HI : LO; + localparam F_LEFT = !(SWAPS[2]) ? HI : LO; + localparam F_RIGHT = (SWAPS[2]) ? HI : LO; + + localparam [HI:LO] A_CONST = A_VAL; + localparam [HI:LO] B_CONST = B_VAL; + localparam [HI:LO] C_CONST = F(A_CONST, B_CONST); + + reg [HI:LO] C_WIRE, C_FUNC; + always @* begin + assert (C_CONST == C_WIRE); + assert (C_CONST == C_FUNC); + end + + initial begin : blk + reg [HI:LO] A_WIRE; + reg [HI:LO] B_WIRE; + reg [D_LEFT:D_RIGHT] D; + reg [E_LEFT:E_RIGHT] E; + reg [F_LEFT:F_RIGHT] F_WIRE; + reg [31:0] i; + A_WIRE = A_VAL; + B_WIRE = B_VAL; + D = A_WIRE; + E = B_WIRE; + F_WIRE = 0; + for (i = LO; i + SPAN < HI; i = i + SPAN) + if (SPAN == 1) + F_WIRE[i] = D[i] && E[i]; + else + F_WIRE[i+:SPAN] = D[i+:SPAN] && E[i+:SPAN]; + C_WIRE = F_WIRE; + C_FUNC = F(A_WIRE, B_WIRE); + end + + function automatic [F_LEFT:F_RIGHT] F( + input [D_LEFT:D_RIGHT] D, + input [E_LEFT:E_RIGHT] E); + reg [31:0] i; + F = 0; + for (i = LO; i + SPAN < HI; i = i + SPAN) + if (SPAN == 1) + F[i] = D[i] && E[i]; + else + F[i+:SPAN] = D[i+:SPAN] && E[i+:SPAN]; + endfunction +endmodule + +module top; + for (genvar hi = 0; hi < 3; hi++) + for (genvar lo = 0; lo <= hi; lo++) + for (genvar span = 1; span <= hi - lo + 1; span++) + for (genvar a_val = 0; a_val < 2 ** (hi - lo + 1); a_val++) + for (genvar b_val = 0; b_val < 2 ** (hi - lo + 1); b_val++) + for (genvar swaps = 0; swaps < 2 ** 3; swaps++) + evil #( + .HI(hi), + .LO(lo), + .SPAN(span), + .A_VAL(a_val), + .B_VAL(b_val), + .SWAPS(swaps) + ) e(); +endmodule diff --git a/tests/verilog/func_upto.ys b/tests/verilog/func_upto.ys new file mode 100644 index 000000000..7a8c53506 --- /dev/null +++ b/tests/verilog/func_upto.ys @@ -0,0 +1,7 @@ +read_verilog -sv func_upto.sv +hierarchy -top top +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -prove-asserts -enable_undef diff --git a/tests/verilog/struct_access.sv b/tests/verilog/struct_access.sv index f13b8dd51..bc91e3f01 100644 --- a/tests/verilog/struct_access.sv +++ b/tests/verilog/struct_access.sv @@ -77,9 +77,8 @@ module top; `CHECK(s.y.a, 1, 0) `CHECK(s.y.b, 1, 1) - // TODO(zachjs): support access to whole sub-structs and unions - // `CHECK(s.x, 2, 0) - // `CHECK(s.y, 2, 1) + `CHECK(s.x, 2, 0) + `CHECK(s.y, 2, 1) assert (fail === 0); end |