3 files changed, 19 insertions, 3 deletions
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index e1f748e26..f55bf01d2 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
-write_ilang
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-min 18 t:LUT4
@@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
-write_ilang
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-min 9 t:LUT4
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index 571edec1d..c32f12315 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
-write_ilang
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_LUT4
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 0c7695089..6e2415ad7 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -53,3 +53,22 @@ assign q = w;
 endmodule
 EOT
 abc9 -lut 4 -dff
+
+
+design -reset
+read_verilog -icells -specify <<EOT
+(* abc9_lut=1, blackbox *)
+module LUT2(input [1:0] i, output o);
+parameter [3:0] mask = 0;
+assign o = i[0] ? (i[1] ? mask[3] : mask[2])
+                : (i[1] ? mask[1] : mask[0]);
+specify
+  (i *> o) = 1;
+endspecify
+endmodule
+
+module top(input [1:0] i, output o);
+LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
+endmodule
+EOT
+abc9