4 files changed, 57 insertions, 6 deletions
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
new file mode 100644
index 000000000..610ae1ffd
--- /dev/null
+++ b/tests/arch/intel_alm/blockram.ys
@@ -0,0 +1,6 @@
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
+synth_intel_alm -family cyclonev
+cd sync_ram_sdp
+select -assert-count 1 t:MISTRAL_M10K
+select -assert-none t:MISTRAL_M10K %% t:* %D
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index 8277e925f..01cc78e1b 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -47,9 +47,9 @@ proc
 equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 3 t:MISTRAL_ALUT5
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT3
+select -assert-count 2 t:MISTRAL_ALUT6
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 
 
 design -load read
@@ -69,9 +69,9 @@ proc
 equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 2 t:MISTRAL_ALUT5
-select -assert-count 4 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT3
+select -assert-count 5 t:MISTRAL_ALUT6
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 
 
 design -load read
diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
new file mode 100644
index 000000000..85318562f
--- /dev/null
+++ b/tests/various/const_arg_loop.v
@@ -0,0 +1,44 @@
+module top;
+	function automatic [31:0] operation1;
+		input [4:0] rounds;
+		input integer num;
+		integer i;
+		begin
+			begin : shadow
+				integer rounds;
+				rounds = 0;
+			end
+			for (i = 0; i < rounds; i = i + 1)
+				num = num * 2;
+			operation1 = num;
+		end
+	endfunction
+
+	function automatic [31:0] operation2;
+		input [4:0] var;
+		input integer num;
+		begin
+			var[0] = var[0] ^ 1;
+			operation2 = num * var;
+		end
+	endfunction
+
+	wire [31:0] a;
+	assign a = 2;
+
+	parameter A = 3;
+
+	wire [31:0] x1;
+	assign x1 = operation1(A, a);
+
+	wire [31:0] x2;
+	assign x2 = operation2(A, a);
+
+// `define VERIFY
+`ifdef VERIFY
+    assert property (a == 2);
+    assert property (A == 3);
+    assert property (x1 == 16);
+    assert property (x2 == 4);
+`endif
+endmodule
diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys
new file mode 100644
index 000000000..b039bda10
--- /dev/null
+++ b/tests/various/const_arg_loop.ys
@@ -0,0 +1 @@
+read_verilog const_arg_loop.v