diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/asicworld/xfirrtl | 1 | ||||
| -rw-r--r-- | tests/simple/task_func.v | 19 | ||||
| -rw-r--r-- | tests/simple/xfirrtl | 2 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 6 |
4 files changed, 23 insertions, 5 deletions
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl index c782a2bd6..08bf4ccd8 100644 --- a/tests/asicworld/xfirrtl +++ b/tests/asicworld/xfirrtl @@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop code_hdl_models_dff_async_reset.v $adff code_hdl_models_tff_async_reset.v $adff code_hdl_models_uart.v $adff -code_specman_switch_fabric.v subfield assignment (bits() <= ...) code_tidbits_asyn_reset.v $adff code_tidbits_reg_seq_example.v $adff code_verilog_tutorial_always_example.v empty module diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v index fa50c1d5c..f6e902f63 100644 --- a/tests/simple/task_func.v +++ b/tests/simple/task_func.v @@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4); assign out3 = test3(in); assign out4 = test4(in); endmodule + +// ------------------------------------------------------------------- + +// https://github.com/YosysHQ/yosys/issues/857 +module task_func_test05(data_in,data_out,clk); + output reg data_out; + input data_in; + input clk; + + task myTask; + output out; + input in; + out = in; + endtask + + always @(posedge clk) begin + myTask(data_out,data_in); + end +endmodule diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 00e89b389..50d693513 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,6 +1,7 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of dff_different_styles.v +dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff @@ -12,7 +13,6 @@ multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff operators.v $pow -paramods.v subfield assignment (bits() <= ...) partsel.v drops modules process.v drops modules realexpr.v drops modules diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 218edf931..84e62e011 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -8,7 +8,7 @@ verbose=false keeprunning=false makejmode=false frontend="verilog" -backend_opts="-noattr -noexpr" +backend_opts="-noattr -noexpr -siminit" autotb_opts="" include_opts="" xinclude_opts="" @@ -49,7 +49,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do r) backend_opts="$backend_opts -norename" ;; e) - backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;; + backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;; f) frontend="$OPTARG" ;; s) @@ -175,7 +175,7 @@ do if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v - $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog + $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v fi fi |