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Diffstat (limited to 'tests/xilinx_ug901/fsm_1.ys')
| -rw-r--r-- | tests/xilinx_ug901/fsm_1.ys | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/tests/xilinx_ug901/fsm_1.ys b/tests/xilinx_ug901/fsm_1.ys deleted file mode 100644 index 192966163..000000000 --- a/tests/xilinx_ug901/fsm_1.ys +++ /dev/null @@ -1,16 +0,0 @@ -read_verilog fsm_1.v -hierarchy -top fsm_1 -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE. -stat -select -assert-count 1 t:BUFG -select -assert-count 4 t:FDRE -select -assert-count 2 t:LUT4 -select -assert-count 2 t:LUT5 -select -assert-count 1 t:LUT6 - -select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D |