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-rw-r--r--tests/various/design.ys18
-rw-r--r--tests/various/design1.ys9
-rw-r--r--tests/various/plugin.sh4
-rw-r--r--tests/various/sim_const.ys13
4 files changed, 38 insertions, 6 deletions
diff --git a/tests/various/design.ys b/tests/various/design.ys
index f13ad8171..a64430dc7 100644
--- a/tests/various/design.ys
+++ b/tests/various/design.ys
@@ -1,9 +1,17 @@
read_verilog <<EOT
+(* blackbox *)
+module bb(input i, output o);
+endmodule
+
+(* whitebox *)
+module wb(input i, output o);
+assign o = ~i;
+endmodule
+
module top(input i, output o);
-assign o = i;
+assign o = ~i;
endmodule
EOT
-design -stash foo
-design -delete foo
-logger -expect error "No saved design 'foo' found!" 1
-design -delete foo
+
+design -stash gate
+design -import gate -as gate
diff --git a/tests/various/design1.ys b/tests/various/design1.ys
new file mode 100644
index 000000000..f13ad8171
--- /dev/null
+++ b/tests/various/design1.ys
@@ -0,0 +1,9 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -delete foo
diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh
index d6d4aee59..2880c8c06 100644
--- a/tests/various/plugin.sh
+++ b/tests/various/plugin.sh
@@ -1,6 +1,8 @@
set -e
rm -f plugin.so
CXXFLAGS=$(../../yosys-config --cxxflags)
-CXXFLAGS=${CXXFLAGS// -I\/usr\/local\/share\/yosys\/include/ -I..\/..\/share\/include}
+DATDIR=$(../../yosys-config --datdir)
+DATDIR=${DATDIR//\//\\\/}
+CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys
new file mode 100644
index 000000000..d778b92cd
--- /dev/null
+++ b/tests/various/sim_const.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+
+module top(input clk, output reg [1:0] q);
+ wire [1:0] x = 2'b10;
+ always @(posedge clk)
+ q <= x & 2'b11;
+endmodule
+EOT
+
+proc
+sim -clock clk -n 1 -w top
+select -assert-count 1 a:init=2'b10 top/q %i
+