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-rw-r--r--tests/various/autoname.ys19
-rw-r--r--tests/various/bug1462.ys11
2 files changed, 19 insertions, 11 deletions
diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys
new file mode 100644
index 000000000..830962e81
--- /dev/null
+++ b/tests/various/autoname.ys
@@ -0,0 +1,19 @@
+read_ilang <<EOT
+autoidx 2
+module \top
+ wire output 3 $y
+ wire input 1 \a
+ wire input 2 \b
+ cell $and \b_$and_B
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a
+ connect \B \b
+ connect \Y $y
+ end
+end
+EOT
+autoname
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
deleted file mode 100644
index 15cab5121..000000000
--- a/tests/various/bug1462.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog << EOF
-module top(...);
-input wire [31:0] A;
-output wire [31:0] P;
-
-assign P = A * 32'h12300000;
-
-endmodule
-EOF
-
-synth_xilinx