5 files changed, 20 insertions, 5 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index ac714665f..a9880c722 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -97,4 +97,5 @@ select -assert-count 3 t:$_DFF_N_
 select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
 clean
 select -assert-count 2 a:init
-select -assert-none w:w w:z %% a:init %D
+select -assert-count 1 w:w a:init %i
+select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
index f55ef2316..8c9fb2926 100644
--- a/tests/various/attrib07_func_call.v
+++ b/tests/various/attrib07_func_call.v
@@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
-  output wire [7:0] out;
+  output reg  [7:0] out;
 
   always @(posedge clk)
     if (rst) out <= 0;
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
index fab1b1bbc..b6809c7c0 100644
--- a/tests/various/constmsk_testmap.v
+++ b/tests/various/constmsk_testmap.v
@@ -1,7 +1,7 @@
 (* techmap_celltype = "$reduce_or" *)
 module my_opt_reduce_or(...);
     parameter A_SIGNED = 0;
-    parameter A_WIDTH = 1;
+    parameter A_WIDTH = 2;
     parameter Y_WIDTH = 1;
 
     input [A_WIDTH-1:0] A;
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
new file mode 100644
index 000000000..afc6d8eb6
--- /dev/null
+++ b/tests/various/printattr.ys
@@ -0,0 +1,14 @@
+logger -expect log ".*cells_not_processed=[01]* .*" 1
+logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+read_verilog <<EOT
+module mux2(a, b, s, y);
+	input a, b, s;
+	output y;
+
+	wire s_n = ~s;
+	wire t0 = s & a;
+	wire t1 = s_n & b;
+	assign y = t0 | t1;
+endmodule
+EOT
+printattrs
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 604c2c976..dc828eda7 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
 endmodule
 
 module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 always @(posedge C) 
@@ -38,7 +38,7 @@ endmodule
 module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
 parameter CLKPOL = 1;
 parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;