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Diffstat (limited to 'tests/ice40/mux.ys')
| -rw-r--r-- | tests/ice40/mux.ys | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 9e3d87b7f..182b49499 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,6 +1,8 @@ read_verilog mux.v -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 20 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |