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-rw-r--r--tests/efinix/latches.ys33
1 files changed, 0 insertions, 33 deletions
diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys
deleted file mode 100644
index 899d024ce..000000000
--- a/tests/efinix/latches.ys
+++ /dev/null
@@ -1,33 +0,0 @@
-read_verilog latches.v
-design -save read
-
-hierarchy -top latchp
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
-cd latchp # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_LUT4
-
-select -assert-none t:EFX_LUT4 %% t:* %D
-
-
-design -load read
-hierarchy -top latchn
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
-cd latchn # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_LUT4
-
-select -assert-none t:EFX_LUT4 %% t:* %D
-
-
-design -load read
-hierarchy -top latchsr
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
-cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:EFX_LUT4
-
-select -assert-none t:EFX_LUT4 %% t:* %D