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Diffstat (limited to 'tests/efinix/add_sub.ys')
| -rw-r--r-- | tests/efinix/add_sub.ys | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys deleted file mode 100644 index 8bd28c68e..000000000 --- a/tests/efinix/add_sub.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:EFX_ADD -select -assert-count 4 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D - |