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-rw-r--r--tests/ecp5/macc.ys10
1 files changed, 0 insertions, 10 deletions
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys
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--- a/tests/ecp5/macc.ys
+++ /dev/null
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-read_verilog macc.v
-proc
-hierarchy -top top
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 41 t:LUT4
-select -assert-count 6 t:CARRY
-select -assert-count 7 t:DFFSR
-select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D