8 files changed, 130 insertions, 10 deletions
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index 12c34415e..e73bfe0b9 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -20,9 +20,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 
-select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
 
 
 design -load read
diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys
new file mode 100644
index 000000000..27a94834e
--- /dev/null
+++ b/tests/arch/xilinx/blockram_params.ys
@@ -0,0 +1,47 @@
+## TODO: Not running equivalence checking because BRAM models does not exists
+##       currently. Checking instance counts instead.
+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+# Anything memory bits < 1024 -> LUTRAM
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
+select -assert-count 4 t:RAM128X1D
+
+# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB36E1
+
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 57b645d19..604acdbfc 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 7 t:MUXCY
 select -assert-count 8 t:XORCY
-select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys
new file mode 100644
index 000000000..0067a822b
--- /dev/null
+++ b/tests/arch/xilinx/dsp_fastfir.ys
@@ -0,0 +1,69 @@
+read_verilog <<EOT
+// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
+module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
+  wire [30:0] _00_;
+  wire [23:0] _01_;
+  wire [11:0] _02_;
+  wire [30:0] _03_;
+  wire [23:0] _04_;
+  wire [30:0] _05_;
+  wire [23:0] _06_;
+  wire [30:0] _07_;
+  wire [23:0] _08_;
+  wire [11:0] _09_;
+  wire [30:0] _10_;
+  wire [23:0] _11_;
+  wire [30:0] _12_;
+  wire [23:0] _13_;
+  wire [11:0] \fir.FILTER[0].tapk.delayed_sample ;
+  reg [30:0] \fir.FILTER[0].tapk.o_acc  = 31'h00000000;
+  wire [11:0] \fir.FILTER[0].tapk.o_sample ;
+  reg [23:0] \fir.FILTER[0].tapk.product ;
+  reg [11:0] \fir.FILTER[0].tapk.tap  = 12'h000;
+  wire [11:0] \fir.FILTER[1].tapk.delayed_sample ;
+  wire [30:0] \fir.FILTER[1].tapk.o_acc ;
+  wire [11:0] \fir.FILTER[1].tapk.o_sample ;
+  reg [23:0] \fir.FILTER[1].tapk.product ;
+  reg [11:0] \fir.FILTER[1].tapk.tap  = 12'h000;
+  input i_ce;
+  input i_clk;
+  input i_reset;
+  input [11:0] i_sample;
+  input [11:0] i_tap;
+  input i_tap_wr;
+  output [30:0] o_result;
+  reg [30:0] o_result;
+  assign _03_ = 31'h00000000 + { \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product  };
+  assign _04_ = $signed(\fir.FILTER[0].tapk.tap ) * $signed(i_sample);
+  always @(posedge i_clk)
+      \fir.FILTER[0].tapk.tap  <= _02_;
+  always @(posedge i_clk)
+      \fir.FILTER[0].tapk.o_acc  <= _00_;
+  always @(posedge i_clk)
+      \fir.FILTER[0].tapk.product  <= _01_;
+  assign _02_ = i_tap_wr ? i_tap : \fir.FILTER[0].tapk.tap ;
+  assign _05_ = i_ce ? _03_ : \fir.FILTER[0].tapk.o_acc ;
+  assign _00_ = i_reset ? 31'h00000000 : _05_;
+  assign _06_ = i_ce ? _04_ : \fir.FILTER[0].tapk.product ;
+  assign _01_ = i_reset ? 24'h000000 : _06_;
+  assign _10_ = \fir.FILTER[0].tapk.o_acc  + { \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product  };
+  assign _11_ = $signed(\fir.FILTER[1].tapk.tap ) * $signed(i_sample);
+  always @(posedge i_clk)
+      \fir.FILTER[1].tapk.tap  <= _09_;
+  always @(posedge i_clk)
+      o_result <= _07_;
+  always @(posedge i_clk)
+      \fir.FILTER[1].tapk.product  <= _08_;
+  assign _09_ = i_tap_wr ? \fir.FILTER[0].tapk.tap  : \fir.FILTER[1].tapk.tap ;
+  assign _12_ = i_ce ? _10_ : o_result;
+  assign _07_ = i_reset ? 31'h00000000 : _12_;
+  assign _13_ = i_ce ? _11_ : \fir.FILTER[1].tapk.product ;
+  assign _08_ = i_reset ? 24'h000000 : _13_;
+  assign \fir.FILTER[1].tapk.o_acc  = o_result;
+endmodule
+EOT
+
+synth_xilinx
+cd fastfir_dynamictaps
+select -assert-count 2 t:DSP48E1
+select -assert-none t:* t:DSP48E1 %d t:BUFG %d
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index d2b481421..2a72c34e8 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -2,7 +2,11 @@ read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index fe7887e8d..c87a8e38b 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -18,9 +18,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalen
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 
-select -assert-none t:LDCE t:LUT1 %% t:* %D
+select -assert-none t:LDCE t:INV %% t:* %D
 
 
 design -load read
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index c0f6da302..d5b5c1a37 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 6 t:LUT2
 select -assert-count 2 t:LUT4
-select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
+select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D
diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh
index 2272679ee..154a29848 100644
--- a/tests/arch/xilinx/macc.sh
+++ b/tests/arch/xilinx/macc.sh
@@ -1,3 +1,3 @@
-../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
+../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
 iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
 vvp -N ./test_macc