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-rw-r--r--tests/anlogic/shifter.ys1
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys
index edd89b344..5eaed30a3 100644
--- a/tests/anlogic/shifter.ys
+++ b/tests/anlogic/shifter.ys
@@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:AL_MAP_SEQ
+
select -assert-none t:AL_MAP_SEQ %% t:* %D