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-rw-r--r--tests/anlogic/mux.ys42
1 files changed, 0 insertions, 42 deletions
diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys
deleted file mode 100644
index 64ed2a2bd..000000000
--- a/tests/anlogic/mux.ys
+++ /dev/null
@@ -1,42 +0,0 @@
-read_verilog mux.v
-design -save read
-
-hierarchy -top mux2
-proc
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:AL_MAP_LUT3
-
-select -assert-none t:AL_MAP_LUT3 %% t:* %D
-
-design -load read
-hierarchy -top mux4
-proc
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:AL_MAP_LUT6
-
-select -assert-none t:AL_MAP_LUT6 %% t:* %D
-
-design -load read
-hierarchy -top mux8
-proc
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 3 t:AL_MAP_LUT4
-select -assert-count 1 t:AL_MAP_LUT6
-
-select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D
-
-design -load read
-hierarchy -top mux16
-proc
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:AL_MAP_LUT6
-
-select -assert-none t:AL_MAP_LUT6 %% t:* %D