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Diffstat (limited to 'tests/anlogic/memory.ys')
| -rw-r--r-- | tests/anlogic/memory.ys | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys deleted file mode 100644 index 8c0ce844e..000000000 --- a/tests/anlogic/memory.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. -#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top - -select -assert-count 8 t:AL_MAP_LUT2 -select -assert-count 8 t:AL_MAP_LUT4 -select -assert-count 8 t:AL_MAP_LUT5 -select -assert-count 36 t:AL_MAP_SEQ -select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D |