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-rw-r--r--techlibs/ice40/arith_map.v10
-rw-r--r--techlibs/ice40/cells_map.v13
-rw-r--r--techlibs/ice40/synth_ice40.cc4
3 files changed, 17 insertions, 10 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 65f28c585..26b24db9e 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,10 +44,18 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
- \$__ICE40_FULL_ADDER carry (
+ \$__ICE40_CARRY_WRAPPER #(
+ // A[0]: 1010 1010 1010 1010
+ // A[1]: 1100 1100 1100 1100
+ // A[2]: 1111 0000 1111 0000
+ // A[3]: 1111 1111 0000 0000
+ .LUT(16'b 0110_1001_1001_0110)
+ ) fadd (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
+ .I0(1'b0),
+ .I3(C[i]),
.CO(CO[i]),
.O(Y[i])
);
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 511b7f6c6..0c10c9ac4 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,8 @@ endmodule
`endif
`ifndef NO_ADDER
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+ parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
@@ -72,13 +73,9 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
);
\$lut #(
.WIDTH(4),
- // A[0]: 1010 1010 1010 1010
- // A[1]: 1100 1100 1100 1100
- // A[2]: 1111 0000 1111 0000
- // A[3]: 1111 1111 0000 0000
- .LUT(16'b 0110_1001_1001_0110)
- ) adder (
- .A({CI,B,A,1'b0}),
+ .LUT(LUT)
+ ) lut (
+ .A({I3,B,A,I0}),
.Y(O)
);
endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 93d5dcbd4..8f4a0f377 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -293,8 +293,10 @@ struct SynthIce40Pass : public ScriptPass
{
if (nocarry)
run("techmap");
- else
+ else {
+ run("ice40_wrapcarry");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+ }
if (retime || help_mode)
run(abc + " -dff", "(only if -retime)");
run("ice40_opt");