diff options
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 22 |
3 files changed, 9 insertions, 16 deletions
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index eee3b418f..ff39ba4fe 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 59fd61cf0..17c5df37d 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,8 +31,10 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) + $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index b13f8d1ee..27e860801 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -94,11 +94,8 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T4; - else begin - MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5])); - MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5])); - MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6])); - end + else + \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q)); end else if (DEPTH > 97 && DEPTH < 128) begin wire T0, T1, T2, T3, T4, T5, T6, T7, T8; @@ -108,11 +105,8 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T6; - else begin - MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5])); - MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5])); - MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6])); - end + else + \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q)); end else if (DEPTH == 128) begin wire T0, T1, T2, T3, T4, T5, T6; @@ -122,12 +116,8 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T6; - else begin - wire T7, T8; - MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5])); - MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5])); - MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6])); - end + else + \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q)); end else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin // Handle cases where fixed-length depth is |