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-rw-r--r--techlibs/common/abc9_map.v2
-rw-r--r--techlibs/common/techmap.v102
-rw-r--r--techlibs/efinix/cells_map.v6
-rw-r--r--techlibs/intel/Makefile.inc2
-rw-r--r--techlibs/intel/arria10gx/cells_arith.v71
-rw-r--r--techlibs/intel/arria10gx/cells_map.v54
-rw-r--r--techlibs/intel/arria10gx/cells_sim.v59
-rw-r--r--techlibs/intel/cyclonev/cells_arith.v71
-rw-r--r--techlibs/intel/cyclonev/cells_map.v126
-rw-r--r--techlibs/intel/synth_intel.cc15
-rw-r--r--techlibs/intel_alm/Makefile.inc2
-rw-r--r--techlibs/intel_alm/cyclonev/cells_sim.v (renamed from techlibs/intel/cyclonev/cells_sim.v)0
-rw-r--r--techlibs/intel_alm/synth_intel_alm.cc2
13 files changed, 50 insertions, 462 deletions
diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
index 6ed90b5f5..b00e0e6a8 100644
--- a/techlibs/common/abc9_map.v
+++ b/techlibs/common/abc9_map.v
@@ -1,5 +1,5 @@
`ifdef DFF
-(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *)
+(* techmap_celltype = "$_DFF_[PN]_" *)
module $_DFF_x_(input C, D, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
parameter _TECHMAP_CELLTYPE_ = "";
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 03c27d49d..2ab28e6e6 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -143,78 +143,46 @@ module _90_shift_shiftx (A, B, Y);
localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
- generate
-`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
- // If $shift/$shiftx only shifts in units of Y_WIDTH
- // (a common pattern created by pmux2shiftx)
- // which is checked by ensuring that all that
- // the appropriate LSBs of B are constant zero,
- // then we can decompose LSB first instead of
- // MSB first
- localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
- if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
- _TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
- _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
- // Halve the size of $shift/$shiftx by $mux-ing A according to
- // the LSB of B, after discarding the zeroed bits
- localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
- localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
- localparam len = Y_WIDTH2 * ((entries+1)/2);
- wire [len-1:0] AA;
- wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){a_padding}}, A};
- genvar i;
- for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
- assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
- wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
- if (_TECHMAP_CELLTYPE_ == "$shift")
- $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- else
- $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- end
- else
-`endif
- begin
- localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
- localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
+ localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
+ localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
- wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
- wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
+ wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
+ wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
- integer i;
- (* force_downto *)
- reg [WIDTH-1:0] buffer;
- reg overflow;
+ integer i;
+ (* force_downto *)
+ reg [WIDTH-1:0] buffer;
+ reg overflow;
- always @* begin
- overflow = 0;
+ always @* begin
+ overflow = 0;
+ buffer = {WIDTH{extbit}};
+ buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
+ buffer[A_WIDTH-1:0] = A;
+
+ if (B_WIDTH > BB_WIDTH) begin
+ if (B_SIGNED) begin
+ for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
+ if (B[i] != B[BB_WIDTH-1])
+ overflow = 1;
+ end else
+ overflow = |B[B_WIDTH-1:BB_WIDTH];
+ if (overflow)
buffer = {WIDTH{extbit}};
- buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
- buffer[A_WIDTH-1:0] = A;
-
- if (B_WIDTH > BB_WIDTH) begin
- if (B_SIGNED) begin
- for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
- if (B[i] != B[BB_WIDTH-1])
- overflow = 1;
- end else
- overflow = |B[B_WIDTH-1:BB_WIDTH];
- if (overflow)
- buffer = {WIDTH{extbit}};
- end
-
- for (i = BB_WIDTH-1; i >= 0; i = i-1)
- if (B[i]) begin
- if (B_SIGNED && i == BB_WIDTH-1)
- buffer = {buffer, {2**i{extbit}}};
- else if (2**i < WIDTH)
- buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
- else
- buffer = {WIDTH{extbit}};
- end
- end
- assign Y = buffer;
end
- endgenerate
+
+ if (B_SIGNED && B[BB_WIDTH-1])
+ buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
+
+ for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
+ if (B[i]) begin
+ if (2**i < WIDTH)
+ buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
+ else
+ buffer = {WIDTH{extbit}};
+ end
+ end
+ assign Y = buffer;
endmodule
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
index 3091ad196..6f6271da2 100644
--- a/techlibs/efinix/cells_map.v
+++ b/techlibs/efinix/cells_map.v
@@ -1,4 +1,4 @@
-(* techmap_celltype = "$_DFFE_PP0P_ $_DFFE_PP0N_ $_DFFE_PP1P_ $_DFFE_PP1N_ $_DFFE_PN0P_ $_DFFE_PN0N_ $_DFFE_PN1P_ $_DFFE_PN1N_ $_DFFE_NP0P_ $_DFFE_NP0N_ $_DFFE_NP1P_ $_DFFE_NP1N_ $_DFFE_NN0P_ $_DFFE_NN0N_ $_DFFE_NN1P_ $_DFFE_NN1N_" *)
+(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
@@ -17,7 +17,7 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
endmodule
-(* techmap_celltype = "$_SDFFE_PP0P_ $_SDFFE_PP0N_ $_SDFFE_PP1P_ $_SDFFE_PP1N_ $_SDFFE_PN0P_ $_SDFFE_PN0N_ $_SDFFE_PN1P_ $_SDFFE_PN1N_ $_SDFFE_NP0P_ $_SDFFE_NP0N_ $_SDFFE_NP1P_ $_SDFFE_NP1N_ $_SDFFE_NN0P_ $_SDFFE_NN0N_ $_SDFFE_NN1P_ $_SDFFE_NN1N_" *)
+(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *)
module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
@@ -36,7 +36,7 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
endmodule
-(* techmap_celltype = "$_SDFFCE_PP0P_ $_SDFFCE_PP0N_ $_SDFFCE_PP1P_ $_SDFFCE_PP1N_ $_SDFFCE_PN0P_ $_SDFFCE_PN0N_ $_SDFFCE_PN1P_ $_SDFFCE_PN1N_ $_SDFFCE_NP0P_ $_SDFFCE_NP0N_ $_SDFFCE_NP1P_ $_SDFFCE_NP1N_ $_SDFFCE_NN0P_ $_SDFFCE_NN0N_ $_SDFFCE_NN1P_ $_SDFFCE_NN1N_" *)
+(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *)
module \$_SDFFCE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index fef6aab77..b06cf5b72 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -8,7 +8,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
# Add the cell models and mappings for the VQM backend
-families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive
+families := max10 cyclone10lp cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v
deleted file mode 100644
index 6a52a0f95..000000000
--- a/techlibs/intel/arria10gx/cells_arith.v
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// NOTE: This is still WIP.
-(* techmap_celltype = "$alu" *)
-module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- (* force_downto *)
- input [A_WIDTH-1:0] A;
- (* force_downto *)
- input [B_WIDTH-1:0] B;
- (* force_downto *)
- output [Y_WIDTH-1:0] X, Y;
-
- input CI, BI;
- //output [Y_WIDTH-1:0] CO;
- output CO;
-
- wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
-
- (* force_downto *)
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- (* force_downto *)
- wire [Y_WIDTH-1:0] AA = A_buf;
- (* force_downto *)
- wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
- //wire [Y_WIDTH:0] C = {CO, CI};
- wire [Y_WIDTH+1:0] COx;
- wire [Y_WIDTH+1:0] C = {COx, CI};
-
- /* Start implementation */
- (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
- genvar i;
- generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
- if(i==Y_WIDTH-1) begin
- (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
- assign CO = COx[Y_WIDTH];
- end
- else
- fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
- end: slice
- endgenerate
- /* End implementation */
- assign X = AA ^ BB;
-
-endmodule
diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v
deleted file mode 100644
index 83f5881da..000000000
--- a/techlibs/intel/arria10gx/cells_map.v
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-// Input buffer map
-module \$__inpad (input I, output O);
- twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
- twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
- (* force_downto *)
- input [WIDTH-1:0] A;
- output Y;
- generate
- if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end else
- if (WIDTH == 2) begin
- twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
- end /*else
- if(WIDTH == 3) begin
- fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
- end else
- if(WIDTH == 4) begin
- fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
- end*/ else
- wire _TECHMAP_FAIL_ = 1;
- endgenerate
-endmodule //
-
-
diff --git a/techlibs/intel/arria10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v
deleted file mode 100644
index e892b377e..000000000
--- a/techlibs/intel/arria10gx/cells_sim.v
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-module VCC (output V);
- assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
- assign G = 1'b0;
-endmodule // GND
-
-/* Altera Arria 10 GX devices Input Buffer Primitive */
-module twentynm_io_ibuf (output o, input i, input ibar);
- assign ibar = ibar;
- assign o = i;
-endmodule // twentynm_io_ibuf
-
-/* Altera Arria 10 GX devices Output Buffer Primitive */
-module twentynm_io_obuf (output o, input i, input oe);
- assign o = i;
- assign oe = oe;
-endmodule // twentynm_io_obuf
-
-/* Altera Arria 10 GX LUT Primitive */
-module twentynm_lcell_comb (output combout, cout, sumout,
- input dataa, datab, datac, datad,
- input datae, dataf, datag, cin,
- input sharein);
-
-parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
-parameter dont_touch = "off";
-parameter lpm_type = "twentynm_lcell_comb";
-parameter shared_arith = "off";
-parameter extended_lut = "off";
-
-// TODO: This is still WIP
-initial begin
- $display("Simulation model is still under investigation\n");
-end
-
-endmodule // twentynm_lcell_comb
-
-
-
diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v
deleted file mode 100644
index 6a52a0f95..000000000
--- a/techlibs/intel/cyclonev/cells_arith.v
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// NOTE: This is still WIP.
-(* techmap_celltype = "$alu" *)
-module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- (* force_downto *)
- input [A_WIDTH-1:0] A;
- (* force_downto *)
- input [B_WIDTH-1:0] B;
- (* force_downto *)
- output [Y_WIDTH-1:0] X, Y;
-
- input CI, BI;
- //output [Y_WIDTH-1:0] CO;
- output CO;
-
- wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
-
- (* force_downto *)
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- (* force_downto *)
- wire [Y_WIDTH-1:0] AA = A_buf;
- (* force_downto *)
- wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
- //wire [Y_WIDTH:0] C = {CO, CI};
- wire [Y_WIDTH+1:0] COx;
- wire [Y_WIDTH+1:0] C = {COx, CI};
-
- /* Start implementation */
- (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
- genvar i;
- generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
- if(i==Y_WIDTH-1) begin
- (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
- assign CO = COx[Y_WIDTH];
- end
- else
- fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
- end: slice
- endgenerate
- /* End implementation */
- assign X = AA ^ BB;
-
-endmodule
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
deleted file mode 100644
index 0041481ab..000000000
--- a/techlibs/intel/cyclonev/cells_map.v
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
-// > Intel FPGA technology mapping. User must first simulate the generated \
-// > netlist before going to test it on board.
-
-// Input buffer map
-module \$__inpad (input I, output O);
- cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
- cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
- (* force_downto *)
- input [WIDTH-1:0] A;
- output Y;
- wire VCC;
- wire GND;
- assign {VCC,GND} = {1'b1,1'b0};
-
- generate
- if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end
- else
- if (WIDTH == 2) begin
- cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(VCC),
- .datad(VCC),
- .datae(VCC),
- .dataf(VCC),
- .datag(VCC));
- end
- else
- if(WIDTH == 3) begin
- cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(A[2]),
- .datad(VCC),
- .datae(VCC),
- .dataf(VCC),
- .datag(VCC));
- end
- else
- if(WIDTH == 4) begin
- cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(A[2]),
- .datad(A[3]),
- .datae(VCC),
- .dataf(VCC),
- .datag(VCC));
- end
- else
- if(WIDTH == 5) begin
- cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(VCC),
- .datag(VCC));
- end
- else
- if(WIDTH == 6) begin
- cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(A[5]),
- .datag(VCC));
- end
- /*else
- if(WIDTH == 7) begin
- TODO: There's not a just 7-input function on Cyclone V, see the following note:
- **Extended LUT Mode**
- Use extended LUT mode to implement a specific set of 7-input functions. The set must
- be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
- [source](Device Interfaces and Integration Basics for Cyclone V Devices).
- end*/
- else
- wire _TECHMAP_FAIL_ = 1;
- endgenerate
-endmodule // lut
-
-
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 090237722..a513528f7 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -36,11 +36,11 @@ struct SynthIntelPass : public ScriptPass {
log("\n");
log("This command runs synthesis for Intel FPGAs.\n");
log("\n");
- log(" -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
+ log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
- log(" Cyclone V and Arria 10 GX devices are experimental.\n");
+ log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
@@ -147,9 +147,11 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
+
+ if (family_opt == "cyclonev")
+ log_cmd_error("Cyclone V synthesis has been moved to synth_intel_alm.\n");
+
if (family_opt != "max10" &&
- family_opt != "arria10gx" &&
- family_opt != "cyclonev" &&
family_opt != "cycloneiv" &&
family_opt != "cycloneive" &&
family_opt != "cyclone10lp")
@@ -216,10 +218,7 @@ struct SynthIntelPass : public ScriptPass {
}
if (check_label("map_luts")) {
- if (family_opt == "arria10gx" || family_opt == "cyclonev")
- run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
- else
- run("abc -lut 4" + string(retime ? " -dff" : ""));
+ run("abc -lut 4" + string(retime ? " -dff" : ""));
run("clean");
}
diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index e36c81c0e..da88762c4 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -14,6 +14,8 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
+$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
+
# RAM
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel_alm/cyclonev/cells_sim.v
index 9b2a10e72..9b2a10e72 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel_alm/cyclonev/cells_sim.v
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 83f0768a3..7ab50ef8f 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -178,7 +178,7 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("begin")) {
if (family_opt == "cyclonev")
- run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
+ run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 06:28:45 +0000