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-rw-r--r--techlibs/xilinx/tests/.gitignore3
-rw-r--r--techlibs/xilinx/tests/bram1.sh3
-rw-r--r--techlibs/xilinx/tests/bram1.v17
-rw-r--r--techlibs/xilinx/tests/bram1_tb.v52
-rw-r--r--techlibs/xilinx/tests/bram2.sh8
-rw-r--r--techlibs/xilinx/tests/bram2.v35
-rw-r--r--techlibs/xilinx/tests/bram2_tb.v56
7 files changed, 163 insertions, 11 deletions
diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore
index bc2f8babf..496b87461 100644
--- a/techlibs/xilinx/tests/.gitignore
+++ b/techlibs/xilinx/tests/.gitignore
@@ -1,3 +1,6 @@
bram1_cmp
bram1.mk
bram1_[0-9]*/
+bram2.log
+bram2_syn.v
+bram2_tb
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
index 1f0359ac9..7451a1b3e 100644
--- a/techlibs/xilinx/tests/bram1.sh
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -56,7 +56,8 @@ echo "Testing..."
${MAKE:-make} -f bram1.mk
echo
-echo "Used rules:" $(grep -h 'Selected rule.*with efficiency' bram1_*/synth.log | gawk '{ print $3; }' | sort -u)
+echo "Used bram types:"
+grep -h 'Mapping to bram type' bram1_*/synth.log | sort | uniq -c
echo "Cleaning up..."
rm -rf bram1_cmp bram1.mk bram1_[0-9]*/
diff --git a/techlibs/xilinx/tests/bram1.v b/techlibs/xilinx/tests/bram1.v
index 034cc18e9..ac7140a04 100644
--- a/techlibs/xilinx/tests/bram1.v
+++ b/techlibs/xilinx/tests/bram1.v
@@ -10,10 +10,27 @@ module bram1 #(
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
+ localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
+ localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
+ localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
+ localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
+
+ localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
+ localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
+ localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
+ localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
+
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
+ initial begin
+ memory[INIT_ADDR_0] <= INIT_DATA_0;
+ memory[INIT_ADDR_1] <= INIT_DATA_1;
+ memory[INIT_ADDR_2] <= INIT_DATA_2;
+ memory[INIT_ADDR_3] <= INIT_DATA_3;
+ end
+
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index 8f854b749..e75dfe31d 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -8,6 +8,16 @@ module bram1_tb #(
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
+ localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
+ localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
+ localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
+ localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
+
+ localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
+ localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
+ localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
+ localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
+
bram1 #(
// .ABITS(ABITS),
// .DBITS(DBITS),
@@ -68,6 +78,11 @@ module bram1_tb #(
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
+ memory[INIT_ADDR_0] = INIT_DATA_0;
+ memory[INIT_ADDR_1] = INIT_DATA_1;
+ memory[INIT_ADDR_2] = INIT_DATA_2;
+ memory[INIT_ADDR_3] = INIT_DATA_3;
+
xorshift64_next;
xorshift64_next;
xorshift64_next;
@@ -84,16 +99,33 @@ module bram1_tb #(
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
- if (DBITS > 64)
- WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
- else
- WR_DATA <= xorshift64_state;
- xorshift64_next;
- WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
- xorshift64_next;
- RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
- WR_EN <= xorshift64_state[55];
- xorshift64_next;
+ if (i == 0) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_0;
+ end else
+ if (i == 1) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_1;
+ end else
+ if (i == 2) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_2;
+ end else
+ if (i == 3) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_3;
+ end else begin
+ if (DBITS > 64)
+ WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
+ else
+ WR_DATA <= xorshift64_state;
+ xorshift64_next;
+ WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
+ xorshift64_next;
+ RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
+ WR_EN <= xorshift64_state[55];
+ xorshift64_next;
+ end
#1; clk <= 1;
#1; clk <= 0;
diff --git a/techlibs/xilinx/tests/bram2.sh b/techlibs/xilinx/tests/bram2.sh
new file mode 100644
index 000000000..5d9c84dac
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2.sh
@@ -0,0 +1,8 @@
+#!/bin/bash
+
+set -ex
+unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
+../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
+iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
+vvp -N bram2_tb
+
diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v
new file mode 100644
index 000000000..0a6013ca6
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2.v
@@ -0,0 +1,35 @@
+module myram(
+ input rd_clk,
+ input [ 7:0] rd_addr,
+ output reg [17:0] rd_data,
+ input wr_clk,
+ input wr_enable,
+ input [ 7:0] wr_addr,
+ input [17:0] wr_data
+);
+ reg [17:0] memory [0:255];
+ integer i;
+
+ function [17:0] hash(input [7:0] k);
+ reg [31:0] x;
+ begin
+ x = {k, ~k, k, ~k};
+ x = x ^ (x << 13);
+ x = x ^ (x >> 17);
+ x = x ^ (x << 5);
+ hash = x;
+ end
+ endfunction
+
+ initial begin
+ for (i = 0; i < 256; i = i+1)
+ memory[i] = hash(i);
+ end
+
+ always @(posedge rd_clk)
+ rd_data <= memory[rd_addr];
+
+ always @(posedge wr_clk)
+ if (wr_enable)
+ memory[wr_addr] <= wr_data;
+endmodule
diff --git a/techlibs/xilinx/tests/bram2_tb.v b/techlibs/xilinx/tests/bram2_tb.v
new file mode 100644
index 000000000..0fe4137c6
--- /dev/null
+++ b/techlibs/xilinx/tests/bram2_tb.v
@@ -0,0 +1,56 @@
+`timescale 1 ns / 1 ps
+
+module testbench;
+ reg rd_clk;
+ reg [ 7:0] rd_addr;
+ wire [17:0] rd_data;
+
+ wire wr_clk = 0;
+ wire wr_enable = 0;
+ wire [ 7:0] wr_addr = 0;
+ wire [17:0] wr_data = 0;
+
+ function [17:0] hash(input [7:0] k);
+ reg [31:0] x;
+ begin
+ x = {k, ~k, k, ~k};
+ x = x ^ (x << 13);
+ x = x ^ (x >> 17);
+ x = x ^ (x << 5);
+ hash = x;
+ end
+ endfunction
+
+ myram uut (
+ .rd_clk (rd_clk ),
+ .rd_addr (rd_addr ),
+ .rd_data (rd_data ),
+ .wr_clk (wr_clk ),
+ .wr_enable(wr_enable),
+ .wr_addr (wr_addr ),
+ .wr_data (wr_data )
+ );
+
+ initial begin
+ rd_clk = 0;
+ #1000;
+ forever #10 rd_clk <= ~rd_clk;
+ end
+
+ integer i;
+ initial begin
+ rd_addr <= 0;
+ @(posedge rd_clk);
+ for (i = 0; i < 256; i=i+1) begin
+ rd_addr <= rd_addr + 1;
+ @(posedge rd_clk);
+ // $display("%3d %3d", i, rd_data);
+ if (hash(i) !== rd_data) begin
+ $display("[%1t] ERROR: addr=%3d, data_mem=%18b, data_ref=%18b", $time, i, rd_data, hash(i));
+ $stop;
+ end
+ end
+ $display("[%1t] Passed bram2 test.", $time);
+ $finish;
+ end
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-03 15:49:23 +0000