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-rw-r--r--techlibs/xilinx/brams_map.v248
1 files changed, 170 insertions, 78 deletions
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index 2e9bba9a9..7ea49158d 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -1,12 +1,14 @@
-module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
+ parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [71:0] A1DATA;
+ input A1EN;
input [8:0] B1ADDR;
input [71:0] B1DATA;
@@ -32,6 +34,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_36.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[63:32]),
@@ -45,7 +48,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -63,15 +66,17 @@ endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
+ parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [35:0] A1DATA;
+ input A1EN;
input [8:0] B1ADDR;
input [35:0] B1DATA;
@@ -94,6 +99,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_18.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[31:16]),
@@ -107,7 +113,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -125,19 +131,21 @@ endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
+ parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
@@ -156,59 +164,102 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
- RAMB36E1 #(
- .RAM_MODE("TDP"),
- .READ_WIDTH_A(CFG_DBITS),
- .READ_WIDTH_B(CFG_DBITS),
- .WRITE_WIDTH_A(CFG_DBITS),
- .WRITE_WIDTH_B(CFG_DBITS),
- .WRITE_MODE_A("READ_FIRST"),
- .WRITE_MODE_B("READ_FIRST"),
- .IS_CLKARDCLK_INVERTED(!CLKPOL2),
- .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
- .SIM_DEVICE("7SERIES")
- ) _TECHMAP_REPLACE_ (
- .DIADI(32'd0),
- .DIPADIP(4'd0),
- .DOADO(DO[31:0]),
- .DOPADOP(DOP[3:0]),
- .ADDRARDADDR(A1ADDR_16),
- .CLKARDCLK(CLK2),
- .ENARDEN(|1),
- .REGCEAREGCE(|1),
- .RSTRAMARSTRAM(|0),
- .RSTREGARSTREG(|0),
- .WEA(4'b0),
-
- .DIBDI(DI),
- .DIPBDIP(DIP),
- .DOBDO(DOBDO),
- .DOPBDOP(DOPBDOP),
- .ADDRBWRADDR(B1ADDR_16),
- .CLKBWRCLK(CLK3),
- .ENBWREN(|1),
- .REGCEB(|0),
- .RSTRAMB(|0),
- .RSTREGB(|0),
- .WEBWE(B1EN_8)
- );
+ generate if (CFG_DBITS > 8) begin
+ RAMB36E1 #(
+ .RAM_MODE("TDP"),
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ .WRITE_MODE_A("READ_FIRST"),
+ .WRITE_MODE_B("READ_FIRST"),
+ .IS_CLKARDCLK_INVERTED(!CLKPOL2),
+ .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_36.vh"
+ .SIM_DEVICE("7SERIES")
+ ) _TECHMAP_REPLACE_ (
+ .DIADI(32'd0),
+ .DIPADIP(4'd0),
+ .DOADO(DO[31:0]),
+ .DOPADOP(DOP[3:0]),
+ .ADDRARDADDR(A1ADDR_16),
+ .CLKARDCLK(CLK2),
+ .ENARDEN(A1EN),
+ .REGCEAREGCE(|1),
+ .RSTRAMARSTRAM(|0),
+ .RSTREGARSTREG(|0),
+ .WEA(4'b0),
+
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
+ .DOBDO(DOBDO),
+ .DOPBDOP(DOPBDOP),
+ .ADDRBWRADDR(B1ADDR_16),
+ .CLKBWRCLK(CLK3),
+ .ENBWREN(|1),
+ .REGCEB(|0),
+ .RSTRAMB(|0),
+ .RSTREGB(|0),
+ .WEBWE(B1EN_8)
+ );
+ end else begin
+ RAMB36E1 #(
+ .RAM_MODE("TDP"),
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ .WRITE_MODE_A("READ_FIRST"),
+ .WRITE_MODE_B("READ_FIRST"),
+ .IS_CLKARDCLK_INVERTED(!CLKPOL2),
+ .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_32.vh"
+ .SIM_DEVICE("7SERIES")
+ ) _TECHMAP_REPLACE_ (
+ .DIADI(32'd0),
+ .DIPADIP(4'd0),
+ .DOADO(DO[31:0]),
+ .DOPADOP(DOP[3:0]),
+ .ADDRARDADDR(A1ADDR_16),
+ .CLKARDCLK(CLK2),
+ .ENARDEN(A1EN),
+ .REGCEAREGCE(|1),
+ .RSTRAMARSTRAM(|0),
+ .RSTREGARSTREG(|0),
+ .WEA(4'b0),
+
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
+ .DOBDO(DOBDO),
+ .DOPBDOP(DOPBDOP),
+ .ADDRBWRADDR(B1ADDR_16),
+ .CLKBWRCLK(CLK3),
+ .ENBWREN(|1),
+ .REGCEB(|0),
+ .RSTRAMB(|0),
+ .RSTREGB(|0),
+ .WEBWE(B1EN_8)
+ );
+ end endgenerate
endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
+ parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
@@ -227,41 +278,82 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
- RAMB18E1 #(
- .RAM_MODE("TDP"),
- .READ_WIDTH_A(CFG_DBITS),
- .READ_WIDTH_B(CFG_DBITS),
- .WRITE_WIDTH_A(CFG_DBITS),
- .WRITE_WIDTH_B(CFG_DBITS),
- .WRITE_MODE_A("READ_FIRST"),
- .WRITE_MODE_B("READ_FIRST"),
- .IS_CLKARDCLK_INVERTED(!CLKPOL2),
- .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
- .SIM_DEVICE("7SERIES")
- ) _TECHMAP_REPLACE_ (
- .DIADI(16'b0),
- .DIPADIP(2'b0),
- .DOADO(DO),
- .DOPADOP(DOP),
- .ADDRARDADDR(A1ADDR_14),
- .CLKARDCLK(CLK2),
- .ENARDEN(|1),
- .REGCEAREGCE(|1),
- .RSTRAMARSTRAM(|0),
- .RSTREGARSTREG(|0),
- .WEA(2'b0),
-
- .DIBDI(DI),
- .DIPBDIP(DIP),
- .DOBDO(DOBDO),
- .DOPBDOP(DOPBDOP),
- .ADDRBWRADDR(B1ADDR_14),
- .CLKBWRCLK(CLK3),
- .ENBWREN(|1),
- .REGCEB(|0),
- .RSTRAMB(|0),
- .RSTREGB(|0),
- .WEBWE(B1EN_4)
- );
+ generate if (CFG_DBITS > 8) begin
+ RAMB18E1 #(
+ .RAM_MODE("TDP"),
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ .WRITE_MODE_A("READ_FIRST"),
+ .WRITE_MODE_B("READ_FIRST"),
+ .IS_CLKARDCLK_INVERTED(!CLKPOL2),
+ .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_18.vh"
+ .SIM_DEVICE("7SERIES")
+ ) _TECHMAP_REPLACE_ (
+ .DIADI(16'b0),
+ .DIPADIP(2'b0),
+ .DOADO(DO),
+ .DOPADOP(DOP),
+ .ADDRARDADDR(A1ADDR_14),
+ .CLKARDCLK(CLK2),
+ .ENARDEN(A1EN),
+ .REGCEAREGCE(|1),
+ .RSTRAMARSTRAM(|0),
+ .RSTREGARSTREG(|0),
+ .WEA(2'b0),
+
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
+ .DOBDO(DOBDO),
+ .DOPBDOP(DOPBDOP),
+ .ADDRBWRADDR(B1ADDR_14),
+ .CLKBWRCLK(CLK3),
+ .ENBWREN(|1),
+ .REGCEB(|0),
+ .RSTRAMB(|0),
+ .RSTREGB(|0),
+ .WEBWE(B1EN_4)
+ );
+ end else begin
+ RAMB18E1 #(
+ .RAM_MODE("TDP"),
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ .WRITE_MODE_A("READ_FIRST"),
+ .WRITE_MODE_B("READ_FIRST"),
+ .IS_CLKARDCLK_INVERTED(!CLKPOL2),
+ .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+ `include "brams_init_16.vh"
+ .SIM_DEVICE("7SERIES")
+ ) _TECHMAP_REPLACE_ (
+ .DIADI(16'b0),
+ .DIPADIP(2'b0),
+ .DOADO(DO),
+ .DOPADOP(DOP),
+ .ADDRARDADDR(A1ADDR_14),
+ .CLKARDCLK(CLK2),
+ .ENARDEN(A1EN),
+ .REGCEAREGCE(|1),
+ .RSTRAMARSTRAM(|0),
+ .RSTREGARSTREG(|0),
+ .WEA(2'b0),
+
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
+ .DOBDO(DOBDO),
+ .DOPBDOP(DOPBDOP),
+ .ADDRBWRADDR(B1ADDR_14),
+ .CLKBWRCLK(CLK3),
+ .ENBWREN(|1),
+ .REGCEB(|0),
+ .RSTRAMB(|0),
+ .RSTREGB(|0),
+ .WEBWE(B1EN_4)
+ );
+ end endgenerate
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-01 10:16:16 +0000