5 files changed, 67 insertions, 3 deletions
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index d2cff0adb..6bee994be 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -56,7 +56,9 @@
 
 (* abc9_box, lib_whitebox *)
 module MISTRAL_FF(
-    input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
+    input DATAIN,
+    (* clkbuf_sink *) input CLK,
+    input ACLR, ENA, SCLR, SLOAD, SDATA,
     output reg Q
 );
 
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v
index aabcd4539..414d1c941 100644
--- a/techlibs/intel_alm/common/megafunction_bb.v
+++ b/techlibs/intel_alm/common/megafunction_bb.v
@@ -662,3 +662,38 @@ input [15:0] parallelterminationcontrol;
 (* iopad_external_pin *) output obar;
 
 endmodule
+
+(* blackbox *)
+module cyclonev_clkena(inclk, ena, enaout, outclk);
+
+parameter clock_type = "auto";
+parameter ena_register_mode = "always enabled";
+parameter lpm_type = "cyclonev_clkena";
+parameter ena_register_power_up = "high";
+parameter disable_mode = "low";
+parameter test_syn = "high";
+
+input inclk;
+input ena;
+output enaout;
+output outclk;
+
+endmodule
+
+(* blackbox *)
+module cyclone10gx_clkena(inclk, ena, enaout, outclk);
+
+parameter clock_type = "auto";
+parameter ena_register_mode = "always enabled";
+parameter lpm_type = "cyclone10gx_clkena";
+parameter ena_register_power_up = "high";
+parameter disable_mode = "low";
+parameter test_syn = "high";
+
+input inclk;
+input ena;
+output enaout;
+output outclk;
+
+endmodule
+
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index e09aafaa2..dbdf69839 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -50,7 +50,9 @@
 // model can be treated as always returning a defined result.
 
 (* abc9_box, lib_whitebox *)
-module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
+    (* clkbuf_sink *) input CLK1,
+    input [4:0] B1ADDR, output B1DATA);
 
 reg [31:0] mem = 32'b0;
 
@@ -83,7 +85,7 @@ module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 parameter CFG_ABITS = 10;
 parameter CFG_DBITS = 10;
 
-input CLK1;
+(* clkbuf_sink *) input CLK1;
 input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
 input [CFG_DBITS-1:0] A1DATA;
 input A1EN, B1EN;
diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v
index e9494a8ee..b1f970a21 100644
--- a/techlibs/intel_alm/common/misc_sim.v
+++ b/techlibs/intel_alm/common/misc_sim.v
@@ -10,3 +10,12 @@ module MISTRAL_IO((* iopad_external_pin *)  inout PAD, input I, input OE, output
 	assign PAD = OE ? I : 1'bz;
 	assign O = PAD;
 endmodule
+
+// Eventually, we should support clock enables and model them here too.
+// For now, CLKENA is used as a basic entry point to global routing.
+module MISTRAL_CLKBUF (
+	input A,
+	(* clkbuf_driver *) output Q
+);
+	assign Q = A;
+endmodule
+\ No newline at end of file
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 964a094dd..57321de77 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -4,6 +4,7 @@
 `define MLAB cyclonev_mlab_cell
 `define IBUF cyclonev_io_ibuf
 `define OBUF cyclonev_io_obuf
+`define CLKENA cyclonev_clkena
 `endif
 `ifdef cyclone10gx
 `define LCELL cyclone10gx_lcell_comb
@@ -11,6 +12,7 @@
 `define MLAB cyclone10gx_mlab_cell
 `define IBUF cyclone10gx_io_ibuf
 `define OBUF cyclone10gx_io_obuf
+`define CLKENA cyclone10gx_clkena
 `endif
 
 module __MISTRAL_VCC(output Q);
@@ -277,3 +279,17 @@ module MISTRAL_IO(output PAD, input I, OE, output O);
     .oe(OE)
 );
 endmodule
+
+module MISTRAL_CLKBUF (input A, output Q);
+`CLKENA #(
+    .clock_type("auto"),
+    .ena_register_mode("always enabled"),
+    .ena_register_power_up("high"),
+    .disable_mode("low"),
+    .test_syn("high")
+) _TECHMAP_REPLACE_ (
+    .inclk(A),
+    .ena(1'b1),
+    .outclk(Q)
+);
+endmodule