diff options
Diffstat (limited to 'passes')
43 files changed, 393 insertions, 391 deletions
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index 7e32da65f..58c95e5ec 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -206,7 +206,7 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) while (true) { - SigSpec A = sigmap(cell->getPort("\\A")); + SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec EN = sigmap(cell->getPort("\\EN")); if (ffmap.count(A) == 0 || ffmap.count(EN) == 0) @@ -223,7 +223,7 @@ struct ChformalPass : public Pass { if (A_map.second != EN_map.second) break; - cell->setPort("\\A", A_map.first); + cell->setPort(ID::A, A_map.first); cell->setPort("\\EN", EN_map.first); } } @@ -233,7 +233,7 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) for (int i = 0; i < mode_arg; i++) { - SigSpec orig_a = cell->getPort("\\A"); + SigSpec orig_a = cell->getPort(ID::A); SigSpec orig_en = cell->getPort("\\EN"); Wire *new_a = module->addWire(NEW_ID); @@ -243,7 +243,7 @@ struct ChformalPass : public Pass { module->addFf(NEW_ID, orig_a, new_a); module->addFf(NEW_ID, orig_en, new_en); - cell->setPort("\\A", new_a); + cell->setPort(ID::A, new_a); cell->setPort("\\EN", new_en); } } diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 7ea0be9ee..4fd43329f 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -207,7 +207,7 @@ struct DesignPass : public Pass { if (import_mode) { for (auto module : copy_src_modules) { - if (module->get_bool_attribute("\\top")) { + if (module->get_bool_attribute(ID::top)) { copy_src_modules.clear(); copy_src_modules.push_back(module); break; @@ -244,7 +244,7 @@ struct DesignPass : public Pass { RTLIL::Module *t = mod->clone(); t->name = prefix; t->design = copy_to_design; - t->attributes.erase("\\top"); + t->attributes.erase(ID::top); copy_to_design->add(t); queue.insert(t); @@ -276,7 +276,7 @@ struct DesignPass : public Pass { RTLIL::Module *t = fmod->clone(); t->name = trg_name; t->design = copy_to_design; - t->attributes.erase("\\top"); + t->attributes.erase(ID::top); copy_to_design->add(t); queue.insert(t); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index e0d428811..c0e07b6e1 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -482,8 +482,8 @@ struct ShowWorker } std::string proc_src = RTLIL::unescape_id(proc->name); - if (proc->attributes.count("\\src") > 0) - proc_src = proc->attributes.at("\\src").decode_string(); + if (proc->attributes.count(ID::src) > 0) + proc_src = proc->attributes.at(ID::src).decode_string(); fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str()); } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index bafafca4e..8856e21c9 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -79,9 +79,9 @@ struct SpliceWorker cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\Y", module->addWire(NEW_ID, sig.size())); - new_sig = cell->getPort("\\Y"); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); + new_sig = cell->getPort(ID::Y); } sliced_signals_cache[sig] = new_sig; @@ -135,10 +135,10 @@ struct SpliceWorker RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->setPort("\\A", new_sig); - cell->setPort("\\B", sig2); - cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); - new_sig = cell->getPort("\\Y"); + cell->setPort(ID::A, new_sig); + cell->setPort(ID::B, sig2); + cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); + new_sig = cell->getPort(ID::Y); } spliced_signals_cache[sig] = new_sig; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index f5a1f17b3..c01ea725c 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -60,8 +60,8 @@ struct SplitnetsWorker new_wire->port_input = wire->port_input; new_wire->port_output = wire->port_output; - if (wire->attributes.count("\\src")) - new_wire->attributes["\\src"] = wire->attributes.at("\\src"); + if (wire->attributes.count(ID::src)) + new_wire->attributes[ID::src] = wire->attributes.at(ID::src); if (wire->attributes.count("\\keep")) new_wire->attributes["\\keep"] = wire->attributes.at("\\keep"); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index c8e4f3981..255b7cdeb 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -116,13 +116,13 @@ struct statdata_t "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", "$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) { - int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0; - int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0; - int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0; + int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0; + int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0; + int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0; cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y})); } else if (cell_type.in("$mux", "$pmux")) - cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y"))); + cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y))); else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr")) cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q"))); } @@ -357,7 +357,7 @@ struct StatPass : public Pass { for (auto mod : design->selected_modules()) { if (!top_mod && design->full_selection()) - if (mod->get_bool_attribute("\\top")) + if (mod->get_bool_attribute(ID::top)) top_mod = mod; statdata_t data(design, mod, width_mode, cell_area, techname); diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index bcc68d6d2..77eec7490 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -59,8 +59,8 @@ struct EquivInductWorker cell_warn_cache.insert(cell); } if (cell->type == "$equiv") { - SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); if (bit_a != bit_b) { int ez_a = satgen.importSigBit(bit_a, step); int ez_b = satgen.importSigBit(bit_b, step); @@ -125,7 +125,7 @@ struct EquivInductWorker if (!ez->solve(new_step_not_consistent)) { log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset)); for (auto cell : workset) - cell->setPort("\\B", cell->getPort("\\A")); + cell->setPort(ID::B, cell->getPort(ID::A)); success_counter += GetSize(workset); return; } @@ -137,10 +137,10 @@ struct EquivInductWorker for (auto cell : workset) { - SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); - log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y")))); + log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y)))); int ez_a = satgen.importSigBit(bit_a, max_seq+1); int ez_b = satgen.importSigBit(bit_b, max_seq+1); @@ -151,7 +151,7 @@ struct EquivInductWorker if (!ez->solve(cond)) { log(" success!\n"); - cell->setPort("\\B", cell->getPort("\\A")); + cell->setPort(ID::B, cell->getPort(ID::A)); success_counter++; } else { log(" failed.\n"); @@ -220,7 +220,7 @@ struct EquivInductPass : public Pass { for (auto cell : module->selected_cells()) if (cell->type == "$equiv") { - if (cell->getPort("\\A") != cell->getPort("\\B")) + if (cell->getPort(ID::A) != cell->getPort(ID::B)) unproven_equiv_cells.insert(cell); } diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 135eaf145..b4d1d7871 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -122,8 +122,8 @@ struct EquivMarkWorker { auto cell = module->cell(cell_name); - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); if (sig_a == sig_b) { for (auto bit : sig_a) @@ -142,8 +142,8 @@ struct EquivMarkWorker if (cell_regions.count(cell->name) || cell->type != "$equiv") continue; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); log_assert(sig_a != sig_b); diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index e06f9515b..5fd7c5418 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -57,7 +57,7 @@ struct EquivMiterWorker for (auto &conn : c->connections()) { if (!ct.cell_input(c->type, conn.first)) continue; - if (c->type == "$equiv" && (conn.first == "\\A") != gold_mode) + if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode) continue; for (auto bit : sigmap(conn.second)) if (bit_to_driver.count(bit)) @@ -213,18 +213,18 @@ struct EquivMiterWorker vector<Cell*> equiv_cells; for (auto c : miter_module->cells()) - if (c->type == "$equiv" && c->getPort("\\A") != c->getPort("\\B")) + if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B)) equiv_cells.push_back(c); for (auto c : equiv_cells) { SigSpec cmp = mode_undef ? - miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx), - miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) : - miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B")); + miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx), + miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) : + miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B)); if (mode_cmp) { - string cmp_name = string("\\cmp") + log_signal(c->getPort("\\Y")); + string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y)); for (int i = 1; i < GetSize(cmp_name); i++) if (cmp_name[i] == '\\') cmp_name[i] = '_'; diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 18b3e7d36..2a339682a 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -114,9 +114,9 @@ struct EquivPurgeWorker continue; } - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); if (sig_a == sig_b) continue; @@ -130,7 +130,7 @@ struct EquivPurgeWorker for (auto bit : sig_y) visited.insert(bit); - cell->setPort("\\Y", make_output(sig_y, cell->name)); + cell->setPort(ID::Y, make_output(sig_y, cell->name)); } SigSpec srcsig; @@ -168,7 +168,7 @@ struct EquivPurgeWorker for (auto cell : module->cells()) if (cell->type == "$equiv") - cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y")))); + cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y)))); module->fixup_ports(); } diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index c5c28c7d9..2a78e5246 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) { - log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y"))); - module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A")); + if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { + log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y))); + module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A)); module->remove(cell); remove_count++; } diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index c2fab26f2..0e5348880 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -90,8 +90,8 @@ struct EquivSimpleWorker bool run_cell() { - SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit(); int ez_context = ez->frozen_literal(); if (satgen.model_undef) @@ -115,9 +115,9 @@ struct EquivSimpleWorker if (verbose) { log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell)); - log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y"))); + log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y))); } else { - log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y"))); + log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y))); } int step = max_seq; @@ -199,7 +199,7 @@ struct EquivSimpleWorker if (!ez->solve(ez_context)) { log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); - equiv_cell->setPort("\\B", equiv_cell->getPort("\\A")); + equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A)); ez->assume(ez->NOT(ez_context)); return true; } @@ -256,7 +256,7 @@ struct EquivSimpleWorker if (GetSize(equiv_cells) > 1) { SigSpec sig; for (auto c : equiv_cells) - sig.append(sigmap(c->getPort("\\Y"))); + sig.append(sigmap(c->getPort(ID::Y))); log(" Grouping SAT models for %s:\n", log_signal(sig)); } @@ -344,8 +344,8 @@ struct EquivSimplePass : public Pass { int unproven_cells_counter = 0; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) { - auto bit = sigmap(cell->getPort("\\Y").as_bit()); + if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) { + auto bit = sigmap(cell->getPort(ID::Y).as_bit()); auto bit_group = bit; if (!nogroup && bit_group.wire) bit_group.offset = 0; diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index b4a93ccf5..ac3af59f6 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -60,7 +60,7 @@ struct EquivStatusPass : public Pass { for (auto cell : module->selected_cells()) if (cell->type == "$equiv") { - if (cell->getPort("\\A") != cell->getPort("\\B")) + if (cell->getPort(ID::A) != cell->getPort(ID::B)) unproven_equiv_cells.push_back(cell); else proven_equiv_cells++; @@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass { log(" Equivalence successfully proven!\n"); } else { for (auto cell : unproven_equiv_cells) - log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort("\\A")), log_signal(cell->getPort("\\B"))); + log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B))); } unproven_count += GetSize(unproven_equiv_cells); diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 6672948b9..ba1fd1d26 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -127,8 +127,8 @@ struct EquivStructWorker for (auto cell : module->selected_cells()) if (cell->type == "$equiv") { - SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); - SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); + SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); equiv_bits.add(sig_b, sig_a); equiv_inputs.insert(sig_a); equiv_inputs.insert(sig_b); @@ -140,9 +140,9 @@ struct EquivStructWorker for (auto cell : module->selected_cells()) if (cell->type == "$equiv") { - SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); - SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); - SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); + SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit()); if (sig_a == sig_b && equiv_inputs.count(sig_y)) { log(" Purging redundant $equiv cell %s.\n", log_id(cell)); module->connect(sig_y, sig_a); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index a1c8067b4..398a79c69 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -55,7 +55,7 @@ ret_false: sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") { + if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) { goto ret_false; } @@ -67,8 +67,8 @@ ret_false: recursion_monitor.insert(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B")); + RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B)); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) { recursion_monitor.erase(cellport.first); @@ -99,18 +99,18 @@ static bool check_state_users(RTLIL::SigSpec sig) RTLIL::Cell *cell = cellport.first; if (muxtree_cells.count(cell) > 0) continue; - if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig) + if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig) continue; - if (cellport.second != "\\A" && cellport.second != "\\B") + if (cellport.second != ID::A && cellport.second != ID::B) return false; - if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y")) + if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y)) return false; for (auto &port_it : cell->connections()) - if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") + if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y) return false; - if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const()) + if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const()) continue; - if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const()) + if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const()) continue; return false; } @@ -120,8 +120,8 @@ static bool check_state_users(RTLIL::SigSpec sig) static void detect_fsm(RTLIL::Wire *wire) { - bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none"; - bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none"; + bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none"; + bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none"; bool has_init_attr = wire->attributes.count("\\init") > 0; bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))); bool looks_like_state_reg = false, looks_like_good_state_reg = false; @@ -133,7 +133,7 @@ static void detect_fsm(RTLIL::Wire *wire) if (wire->width <= 1) { if (has_fsm_encoding_attr) { log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire)); - wire->attributes.erase("\\fsm_encoding"); + wire->attributes.erase(ID::fsm_encoding); } return; } @@ -234,7 +234,7 @@ static void detect_fsm(RTLIL::Wire *wire) if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting) { log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire)); - wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); + wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto"); } else if (looks_like_state_reg) diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 1610ec751..172449649 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -51,32 +51,32 @@ struct FsmExpand return true; if (cell->type.in("$mux", "$pmux")) - if (cell->getPort("\\A").size() < 2) + if (cell->getPort(ID::A).size() < 2) return true; int in_bits = 0; RTLIL::SigSpec new_signals; - if (cell->hasPort("\\A")) { - in_bits += GetSize(cell->getPort("\\A")); - new_signals.append(assign_map(cell->getPort("\\A"))); + if (cell->hasPort(ID::A)) { + in_bits += GetSize(cell->getPort(ID::A)); + new_signals.append(assign_map(cell->getPort(ID::A))); } - if (cell->hasPort("\\B")) { - in_bits += GetSize(cell->getPort("\\B")); - new_signals.append(assign_map(cell->getPort("\\B"))); + if (cell->hasPort(ID::B)) { + in_bits += GetSize(cell->getPort(ID::B)); + new_signals.append(assign_map(cell->getPort(ID::B))); } - if (cell->hasPort("\\S")) { - in_bits += GetSize(cell->getPort("\\S")); - new_signals.append(assign_map(cell->getPort("\\S"))); + if (cell->hasPort(ID::S)) { + in_bits += GetSize(cell->getPort(ID::S)); + new_signals.append(assign_map(cell->getPort(ID::S))); } if (in_bits > 8) return false; - if (cell->hasPort("\\Y")) - new_signals.append(assign_map(cell->getPort("\\Y"))); + if (cell->hasPort(ID::Y)) + new_signals.append(assign_map(cell->getPort(ID::Y))); new_signals.sort_and_unify(); new_signals.remove_const(); @@ -106,7 +106,7 @@ struct FsmExpand if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; for (auto &p : c->connections()) { - if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y") + if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y) goto next_cell; } if (!is_cell_merge_candidate(c)) { @@ -159,12 +159,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->hasPort("\\A")) - A = assign_map(cell->getPort("\\A")); - if (cell->hasPort("\\B")) - B = assign_map(cell->getPort("\\B")); - if (cell->hasPort("\\S")) - S = assign_map(cell->getPort("\\S")); + if (cell->hasPort(ID::A)) + A = assign_map(cell->getPort(ID::A)); + if (cell->hasPort(ID::B)) + B = assign_map(cell->getPort(ID::B)); + if (cell->hasPort(ID::S)) + S = assign_map(cell->getPort(ID::S)); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 0f7b4d106..354ad87eb 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -70,15 +70,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") { + if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); - RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S")); - RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); RTLIL::SigSpec sig_aa = sig; sig_aa.replace(sig_y, sig_a); @@ -320,14 +320,14 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_b; - if (cell->hasPort("\\B")) - sig_b = assign_map(cell->getPort("\\B")); - RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); - if (cellport.second == "\\A" && !sig_b.is_fully_const()) + if (cell->hasPort(ID::B)) + sig_b = assign_map(cell->getPort(ID::B)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + if (cellport.second == ID::A && !sig_b.is_fully_const()) continue; - if (cellport.second == "\\B" && !sig_a.is_fully_const()) + if (cellport.second == ID::B && !sig_a.is_fully_const()) continue; log(" found ctrl output: %s\n", log_signal(sig_y)); ctrl_out.append(sig_y); @@ -382,7 +382,7 @@ static void extract_fsm(RTLIL::Wire *wire) // rename original state wire module->wires_.erase(wire->name); - wire->attributes.erase("\\fsm_encoding"); + wire->attributes.erase(ID::fsm_encoding); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); module->wires_[wire->name] = wire; @@ -442,15 +442,15 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } - if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") && - cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) && + cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } } if (cell->type == "$pmux") { - RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S")); + RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S)); for (auto &bit1 : sel_sig) for (auto &bit2 : sel_sig) if (bit1 != bit2) @@ -460,7 +460,7 @@ struct FsmExtractPass : public Pass { std::vector<RTLIL::Wire*> wire_list; for (auto &wire_it : module->wires_) - if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") + if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none") if (design->selected(module, wire_it.second)) wire_list.push_back(wire_it.second); for (auto wire : wire_list) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 80913fda8..13231cd25 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -75,9 +75,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const and_sig.append(RTLIL::SigSpec(eq_wire)); RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->setPort("\\A", eq_sig_a); - eq_cell->setPort("\\B", eq_sig_b); - eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire)); + eq_cell->setPort(ID::A, eq_sig_a); + eq_cell->setPort(ID::B, eq_sig_b); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); @@ -103,8 +103,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const and_sig.append(RTLIL::SigSpec(or_wire)); RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->setPort("\\A", or_sig); - or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire)); + or_cell->setPort(ID::A, or_sig); + or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire)); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -119,9 +119,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(RTLIL::SigSpec(and_wire)); RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and"); - and_cell->setPort("\\A", and_sig.extract(0, 1)); - and_cell->setPort("\\B", and_sig.extract(1, 1)); - and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire)); + and_cell->setPort(ID::A, and_sig.extract(0, 1)); + and_cell->setPort(ID::B, and_sig.extract(1, 1)); + and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire)); and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -142,8 +142,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const if (cases_vector.size() > 1) { RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->setPort("\\A", cases_vector); - or_cell->setPort("\\Y", output); + or_cell->setPort(ID::A, cases_vector); + or_cell->setPort(ID::Y, output); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -213,9 +213,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) encoding_is_onehot = false; RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->setPort("\\A", sig_a); - eq_cell->setPort("\\B", sig_b); - eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i)); + eq_cell->setPort(ID::A, sig_a); + eq_cell->setPort(ID::B, sig_b); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -286,10 +286,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux"); - mux_cell->setPort("\\A", sig_a); - mux_cell->setPort("\\B", sig_b); - mux_cell->setPort("\\S", sig_s); - mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire)); + mux_cell->setPort(ID::A, sig_a); + mux_cell->setPort(ID::B, sig_b); + mux_cell->setPort(ID::S, sig_s); + mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire)); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index fa1ff48cc..1ade371d5 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -53,7 +53,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding) { - std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto"; + std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto"; log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3f4fe502d..a7db703c8 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -168,7 +168,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // reprocess the module: if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) { for (auto wire : module->wires()) { - if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface")) + if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) has_interface_ports = true; } } @@ -177,7 +177,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module; for (auto cell : module->cells()) { - if(cell->get_bool_attribute("\\is_interface")) { + if(cell->get_bool_attribute(ID::is_interface)) { RTLIL::Module *intf_module = design->module(cell->type); interfaces_in_module[cell->name] = intf_module; } @@ -253,7 +253,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to // some lists, so that the ports for sub-modules can be replaced further down: for (auto &conn : cell->connections()) { - if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list + if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type"); //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) //} @@ -264,7 +264,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &d : interface_modport_pool) { interface_modport = "\\" + d; } - if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module + if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name interface_name_str = "\\" + interface_name_str; @@ -370,7 +370,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) { // If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:", // so that the signals of the interface are added to the parent module. - if (mod->get_bool_attribute("\\is_interface")) { + if (mod->get_bool_attribute(ID::is_interface)) { goto handle_interface_instance; } continue; @@ -384,8 +384,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter // an interface instance: - if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) { - cell->set_bool_attribute("\\is_interface"); + if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute("\\module_not_derived")) { + cell->set_bool_attribute(ID::is_interface); RTLIL::Module *derived_module = design->module(cell->type); interfaces_in_module[cell->name] = derived_module; did_something = true; @@ -475,7 +475,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) // safe to delete all of the remaining dummy interface ports: pool<RTLIL::Wire*> del_wires; for(auto wire : mod->wires()) { - if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface")) { + if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) { del_wires.insert(wire); } } @@ -532,11 +532,11 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod) { - if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top")) + if(top_mod != NULL && top_mod->get_bool_attribute(ID::initial_top)) return top_mod; else { for (auto mod : design->modules()) { - if (mod->get_bool_attribute("\\top")) { + if (mod->get_bool_attribute(ID::top)) { return mod; } } @@ -814,7 +814,7 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr) for (auto mod : design->modules()) - if (mod->get_bool_attribute("\\top")) + if (mod->get_bool_attribute(ID::top)) top_mod = mod; if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) { @@ -860,9 +860,9 @@ struct HierarchyPass : public Pass { if (top_mod != NULL) { for (auto mod : design->modules()) if (mod == top_mod) - mod->attributes["\\initial_top"] = RTLIL::Const(1); + mod->attributes[ID::initial_top] = RTLIL::Const(1); else - mod->attributes.erase("\\initial_top"); + mod->attributes.erase(ID::initial_top); } bool did_something = true; @@ -915,10 +915,10 @@ struct HierarchyPass : public Pass { if (top_mod != NULL) { for (auto mod : design->modules()) { if (mod == top_mod) - mod->attributes["\\top"] = RTLIL::Const(1); + mod->attributes[ID::top] = RTLIL::Const(1); else - mod->attributes.erase("\\top"); - mod->attributes.erase("\\initial_top"); + mod->attributes.erase(ID::top); + mod->attributes.erase(ID::initial_top); } } @@ -983,8 +983,8 @@ struct HierarchyPass : public Pass { { for (auto module : design->modules()) for (auto wire : module->wires()) - if (wire->port_input && wire->attributes.count("\\defaultvalue")) - defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); + if (wire->port_input && wire->attributes.count(ID::defaultvalue)) + defaults_db[module->name][wire->name] = wire->attributes.at(ID::defaultvalue); } // Process SV implicit wildcard port connections std::set<Module*> blackbox_derivatives; @@ -1071,11 +1071,11 @@ struct HierarchyPass : public Pass { for (auto wire : module->wires()) { - if (wire->get_bool_attribute("\\wand")) { + if (wire->get_bool_attribute(ID::wand)) { wand_map[wire] = SigSpec(); wand_wor_index.insert(wire); } - if (wire->get_bool_attribute("\\wor")) { + if (wire->get_bool_attribute(ID::wor)) { wor_map[wire] = SigSpec(); wand_wor_index.insert(wire); } diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index ad3220918..18fa59ff8 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -64,7 +64,7 @@ struct UniquifyPass : public Pass { for (auto module : design->selected_modules()) { - if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute("\\top")) + if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute(ID::top)) continue; for (auto cell : module->selected_cells()) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index be4b3c100..abbffa7d6 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -189,9 +189,9 @@ struct MemoryDffWorker do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); - sig_data = sigmap(mux->getPort("\\Y")); - en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A))); + sig_data = sigmap(mux->getPort(ID::Y)); + en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S)); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); for (auto bit : sig_data) @@ -259,12 +259,12 @@ struct MemoryDffWorker if (cell->type == "$dff") dff_cells.push_back(cell); if (cell->type == "$mux") { - mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; - mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; + mux_cells_a[sigmap(cell->getPort(ID::A))] = cell; + mux_cells_b[sigmap(cell->getPort(ID::B))] = cell; } - if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_y = cell->getPort("\\Y"); + if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort(ID::A)) == 1)) { + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_y = cell->getPort(ID::Y); if (cell->type == "$not") sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); if (cell->type == "$logic_not") diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 65bccb5ef..b17db372a 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -248,15 +248,15 @@ struct MemoryMapWorker { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->setPort("\\Y", rd_signals[k]); - c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + c->setPort(ID::Y, rd_signals[k]); + c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); + c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - next_rd_signals.push_back(c->getPort("\\A")); - next_rd_signals.push_back(c->getPort("\\B")); + next_rd_signals.push_back(c->getPort(ID::A)); + next_rd_signals.push_back(c->getPort(ID::B)); } next_rd_signals.swap(rd_signals); @@ -309,21 +309,21 @@ struct MemoryMapWorker c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", w); - c->setPort("\\B", wr_bit); + c->setPort(ID::A, w); + c->setPort(ID::B, wr_bit); w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->setPort("\\Y", RTLIL::SigSpec(w)); + c->setPort(ID::Y, RTLIL::SigSpec(w)); } RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->setPort("\\A", sig.extract(wr_offset, wr_width)); - c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); - c->setPort("\\S", RTLIL::SigSpec(w)); + c->setPort(ID::A, sig.extract(wr_offset, wr_width)); + c->setPort(ID::B, wr_data.extract(wr_offset, wr_width)); + c->setPort(ID::S, RTLIL::SigSpec(w)); w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->setPort("\\Y", w); + c->setPort(ID::Y, w); sig.replace(wr_offset, w); wr_offset += wr_width; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b33882595..6dbd32cb3 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -64,18 +64,18 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); - std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); - std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A)); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B)); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S)); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) { - RTLIL::SigSpec new_b = cell->getPort("\\B"); + RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->setPort("\\B", new_b); + cell->setPort(ID::B, new_b); } return false; } @@ -90,9 +90,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) { - RTLIL::SigSpec new_b = cell->getPort("\\B"); + RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->setPort("\\B", new_b); + cell->setPort(ID::B, new_b); } } @@ -101,9 +101,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) { - RTLIL::SigSpec new_a = cell->getPort("\\A"); + RTLIL::SigSpec new_a = cell->getPort(ID::A); new_a.replace(bit_idx, RTLIL::State::Sx); - cell->setPort("\\A", new_a); + cell->setPort(ID::A, new_a); } return false; @@ -157,10 +157,10 @@ struct MemoryShareWorker if (cell->type.in("$mux", "$pmux")) { - std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); - std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); - std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A)); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B)); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S)); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -687,18 +687,18 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->getPort("\\Y"), sig_b); + sigmap_xmux.add(cell->getPort(ID::Y), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->getPort("\\Y"), sig_a); + sigmap_xmux.add(cell->getPort(ID::Y), sig_a); } if (cell->type.in("$mux", "$pmux")) { - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i); } diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index 0053c8872..ebe6f62d5 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -40,8 +40,8 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER"); pm.module->swap_names(cell, st.carry); - cell->setPort("\\A", st.carry->getPort("\\I0")); - cell->setPort("\\B", st.carry->getPort("\\I1")); + cell->setPort(ID::A, st.carry->getPort("\\I0")); + cell->setPort(ID::B, st.carry->getPort("\\I1")); auto CI = st.carry->getPort("\\CI"); cell->setPort("\\CI", CI); cell->setPort("\\CO", st.carry->getPort("\\CO")); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index c606deb88..12c21754c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, for (auto cell : mod->cells()) { - if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal) - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal) + return check_signal(mod, cell->getPort(ID::A), ref, polarity); - if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal) - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal) + return check_signal(mod, cell->getPort(ID::A), ref, polarity); - if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) { + if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } - if (cell->type == "$not" && cell->getPort("\\Y") == signal) { + if (cell->type == "$not" && cell->getPort(ID::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } - if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) { - if (cell->getPort("\\A").is_fully_const()) { - if (!cell->getPort("\\A").as_bool()) + if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) { + if (cell->getPort(ID::A).is_fully_const()) { + if (!cell->getPort(ID::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\B"), ref, polarity); + return check_signal(mod, cell->getPort(ID::B), ref, polarity); } - if (cell->getPort("\\B").is_fully_const()) { - if (!cell->getPort("\\B").as_bool()) + if (cell->getPort(ID::B).is_fully_const()) { + if (!cell->getPort(ID::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } } - if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) { - if (cell->getPort("\\A").is_fully_const()) { - if (cell->getPort("\\A").as_bool()) + if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) { + if (cell->getPort(ID::A).is_fully_const()) { + if (cell->getPort(ID::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\B"), ref, polarity); + return check_signal(mod, cell->getPort(ID::B), ref, polarity); } - if (cell->getPort("\\B").is_fully_const()) { - if (cell->getPort("\\B").as_bool()) + if (cell->getPort(ID::B).is_fully_const()) { + if (cell->getPort(ID::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 519d35cd6..669601031 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -79,8 +79,8 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_low_signals); - cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID)); + cell->setPort(ID::A, sync_low_signals); + cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { @@ -88,9 +88,9 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_low_signals); - cell->setPort("\\Y", mod->addWire(NEW_ID)); - sync_high_signals.append(cell->getPort("\\Y")); + cell->setPort(ID::A, sync_low_signals); + cell->setPort(ID::Y, mod->addWire(NEW_ID)); + sync_high_signals.append(cell->getPort(ID::Y)); } if (sync_high_signals.size() > 1) { @@ -98,30 +98,30 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_high_signals); - cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID)); + cell->setPort(ID::A, sync_high_signals); + cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID)); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->setPort("\\A", sync_value); - inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); + inv_cell->setPort(ID::A, sync_value); + inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->setPort("\\A", sig_sr_set); - mux_set_cell->setPort("\\B", sync_value); - mux_set_cell->setPort("\\S", sync_high_signals); - mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); + mux_set_cell->setPort(ID::A, sig_sr_set); + mux_set_cell->setPort(ID::B, sync_value); + mux_set_cell->setPort(ID::S, sync_high_signals); + mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->setPort("\\A", sig_sr_clr); - mux_clr_cell->setPort("\\B", sync_value_inv); - mux_clr_cell->setPort("\\S", sync_high_signals); - mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); + mux_clr_cell->setPort(ID::A, sig_sr_clr); + mux_clr_cell->setPort(ID::B, sync_value_inv); + mux_clr_cell->setPort(ID::S, sync_high_signals); + mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; @@ -157,22 +157,22 @@ void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->setPort("\\A", sig_set); - inv_set->setPort("\\Y", sig_set_inv); + inv_set->setPort(ID::A, sig_set); + inv_set->setPort(ID::Y, sig_set_inv); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set); - mux_sr_set->setPort("\\Y", sig_sr_set); - mux_sr_set->setPort("\\S", set); + mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); + mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set); + mux_sr_set->setPort(ID::Y, sig_sr_set); + mux_sr_set->setPort(ID::S, set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv); - mux_sr_clr->setPort("\\Y", sig_sr_clr); - mux_sr_clr->setPort("\\S", set); + mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); + mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv); + mux_sr_clr->setPort(ID::Y, sig_sr_clr); + mux_sr_clr->setPort(ID::S, set); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -309,9 +309,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", inputs); - cell->setPort("\\B", compare); - cell->setPort("\\Y", sync_level->signal); + cell->setPort(ID::A, inputs); + cell->setPort(ID::B, compare); + cell->setPort(ID::Y, sync_level->signal); many_async_rules.clear(); } diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index a0c8351b6..446140ffd 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -44,14 +44,14 @@ struct proc_dlatch_db_t { if (cell->type.in("$mux", "$pmux")) { - auto sig_y = sigmap(cell->getPort("\\Y")); + auto sig_y = sigmap(cell->getPort(ID::Y)); for (int i = 0; i < GetSize(sig_y); i++) mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i); pool<SigBit> mux_srcbits_pool; - for (auto bit : sigmap(cell->getPort("\\A"))) + for (auto bit : sigmap(cell->getPort(ID::A))) mux_srcbits_pool.insert(bit); - for (auto bit : sigmap(cell->getPort("\\B"))) + for (auto bit : sigmap(cell->getPort(ID::B))) mux_srcbits_pool.insert(bit); vector<SigBit> mux_srcbits_vec; @@ -180,9 +180,9 @@ struct proc_dlatch_db_t Cell *cell = it->second.first; int index = it->second.second; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); int width = GetSize(sig_a); pool<int> children; @@ -190,9 +190,9 @@ struct proc_dlatch_db_t int n = find_mux_feedback(sig_a[index], needle, set_undef); if (n != false_node) { if (set_undef && sig_a[index] == needle) { - SigSpec sig = cell->getPort("\\A"); + SigSpec sig = cell->getPort(ID::A); sig[index] = State::Sx; - cell->setPort("\\A", sig); + cell->setPort(ID::A, sig); } for (int i = 0; i < GetSize(sig_s); i++) n = make_inner(sig_s[i], State::S0, n); @@ -203,9 +203,9 @@ struct proc_dlatch_db_t n = find_mux_feedback(sig_b[i*width + index], needle, set_undef); if (n != false_node) { if (set_undef && sig_b[i*width + index] == needle) { - SigSpec sig = cell->getPort("\\B"); + SigSpec sig = cell->getPort(ID::B); sig[i*width + index] = State::Sx; - cell->setPort("\\B", sig); + cell->setPort(ID::B, sig); } children.insert(make_inner(sig_s[i], State::S1, n)); } @@ -257,9 +257,9 @@ struct proc_dlatch_db_t void fixup_mux(Cell *cell) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); - SigSpec sig_s = cell->getPort("\\S"); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_s = cell->getPort(ID::S); SigSpec sig_any_valid_b; SigSpec sig_new_b, sig_new_s; @@ -278,7 +278,7 @@ struct proc_dlatch_db_t } if (sig_a.is_fully_undef() && !sig_any_valid_b.empty()) - cell->setPort("\\A", sig_any_valid_b); + cell->setPort(ID::A, sig_any_valid_b); if (GetSize(sig_new_s) == 1) { cell->type = "$mux"; @@ -288,8 +288,8 @@ struct proc_dlatch_db_t cell->setParam("\\S_WIDTH", GetSize(sig_new_s)); } - cell->setPort("\\B", sig_new_b); - cell->setPort("\\S", sig_new_s); + cell->setPort(ID::B, sig_new_b); + cell->setPort(ID::S, sig_new_s); } void fixup_muxes() diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index d029282fd..11c7d745f 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -147,7 +147,7 @@ struct SnippetSwCache void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs) { cell->attributes = sw->attributes; - cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src")); + cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src)); } RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) @@ -188,9 +188,9 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->setPort("\\A", sig); - eq_cell->setPort("\\B", comp); - eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); + eq_cell->setPort(ID::A, sig); + eq_cell->setPort(ID::B, comp); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -211,8 +211,8 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->setPort("\\A", cmp_wire); - any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire)); + any_cell->setPort(ID::A, cmp_wire); + any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -243,10 +243,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s apply_attrs(mux_cell, sw, cs); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->setPort("\\A", else_signal); - mux_cell->setPort("\\B", when_signal); - mux_cell->setPort("\\S", ctrl_sig); - mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire)); + mux_cell->setPort(ID::A, else_signal); + mux_cell->setPort(ID::B, when_signal); + mux_cell->setPort(ID::S, ctrl_sig); + mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(last_mux_cell != NULL); - log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); + log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size()); - if (when_signal == last_mux_cell->getPort("\\A")) + if (when_signal == last_mux_cell->getPort(ID::A)) return; RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S"); + RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S); new_s.append(ctrl_sig); - last_mux_cell->setPort("\\S", new_s); + last_mux_cell->setPort(ID::S, new_s); - RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B"); + RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B); new_b.append(when_signal); - last_mux_cell->setPort("\\B", new_b); + last_mux_cell->setPort(ID::B, new_b); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size(); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort(ID::S).size(); } const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw) @@ -281,7 +281,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul { pool<SigBit> bits; - if (sw->get_bool_attribute("\\full_case")) + if (sw->get_bool_attribute(ID::full_case)) { bool first_case = true; @@ -337,7 +337,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d std::vector<int> pgroups(sw->cases.size()); bool is_simple_parallel_case = true; - if (!sw->get_bool_attribute("\\parallel_case")) { + if (!sw->get_bool_attribute(ID::parallel_case)) { if (!swpara.count(sw)) { pool<Const> case_values; for (size_t i = 0; i < sw->cases.size(); i++) { diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index caf938a74..8d11447f6 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -38,7 +38,7 @@ struct PruneWorker pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected) { pool<RTLIL::SigBit> all_assigned; - bool full_case = sw->get_bool_attribute("\\full_case"); + bool full_case = sw->get_bool_attribute(ID::full_case); bool first = true; for (auto it : sw->cases) { if (it->compare.empty()) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 4f40be446..6afaf25d1 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -62,8 +62,8 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter) pool.take_all(); } - if (pool.empty() && !sw->get_bool_attribute("\\full_case")) { - sw->set_bool_attribute("\\full_case"); + if (pool.empty() && !sw->get_bool_attribute(ID::full_case)) { + sw->set_bool_attribute(ID::full_case); full_case_counter++; } } diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 3b432c461..b4adb1ab3 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -57,9 +57,9 @@ struct AssertpmuxWorker int width = cell->getParam("\\WIDTH").as_int(); int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); for (int i = 0; i < numports; i++) { SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width); @@ -98,12 +98,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S")); + muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S)); else - muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1]; + muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx]))); + output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); } output.sort_and_unify(); @@ -151,7 +151,7 @@ struct AssertpmuxWorker int swidth = pmux->getParam("\\S_WIDTH").as_int(); int cntbits = ceil_log2(swidth+1); - SigSpec sel = pmux->getPort("\\S"); + SigSpec sel = pmux->getPort(ID::S); SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) @@ -164,7 +164,7 @@ struct AssertpmuxWorker assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); if (!flag_always) - assert_en.append(get_activation(pmux->getPort("\\Y"))); + assert_en.append(get_activation(pmux->getPort(ID::Y))); if (GetSize(assert_en) == 0) assert_en = State::S1; @@ -174,8 +174,8 @@ struct AssertpmuxWorker Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); - if (pmux->attributes.count("\\src") != 0) - assert_cell->attributes["\\src"] = pmux->attributes.at("\\src"); + if (pmux->attributes.count(ID::src) != 0) + assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src); } }; diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 24aba22f3..cc16a767c 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -336,7 +336,7 @@ struct Clk2fflogicPass : public Pass { ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) { SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); - SigSpec setval = cell->getPort("\\S"); + SigSpec setval = cell->getPort(ID::S); SigSpec clrval = cell->getPort("\\R"); if (cell->type[9] != 'P') diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 8fb47f357..4f0ba44f6 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -562,8 +562,8 @@ struct ExposePass : public Pass { c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->setPort("\\A", info.sig_clk); - c->setPort("\\Y", wire_c); + c->setPort(ID::A, info.sig_clk); + c->setPort(ID::Y, wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -578,8 +578,8 @@ struct ExposePass : public Pass { c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->setPort("\\A", info.sig_arst); - c->setPort("\\Y", wire_r); + c->setPort(ID::A, info.sig_arst); + c->setPort(ID::Y, wire_r); } RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 00c098542..18eeb37b5 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -359,7 +359,7 @@ struct FmcombinePass : public Pass { Cell *cell = module->addCell(combined_cell_name, worker.combined_type); cell->attributes = gold_cell->attributes; - cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src")); + cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src)); log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell)); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 54016e528..020e2a74c 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -635,8 +635,8 @@ struct FreduceWorker batches.push_back(outputs); bits_full_total += outputs.size(); } - if (inv_mode && cell->type == "$_NOT_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y")))); + if (inv_mode && cell->type == ID($_NOT_)) + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y)))); } int bits_count = 0; @@ -732,8 +732,8 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_"); - inv_cell->setPort("\\A", grp[0].bit); - inv_cell->setPort("\\Y", inv_sig); + inv_cell->setPort(ID::A, grp[0].bit); + inv_cell->setPort(ID::Y, inv_sig); } module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 742433935..f5bc251c2 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -155,9 +155,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i)); - eqx_cell->setPort("\\B", RTLIL::State::Sx); - eqx_cell->setPort("\\Y", gold_x.extract(i, 1)); + eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i)); + eqx_cell->setPort(ID::B, RTLIL::State::Sx); + eqx_cell->setPort(ID::Y, gold_x.extract(i, 1)); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width); @@ -169,9 +169,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->setPort("\\A", w_gold); - or_gold_cell->setPort("\\B", gold_x); - or_gold_cell->setPort("\\Y", gold_masked); + or_gold_cell->setPort(ID::A, w_gold); + or_gold_cell->setPort(ID::B, gold_x); + or_gold_cell->setPort(ID::Y, gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width; @@ -179,9 +179,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->setPort("\\A", w_gate); - or_gate_cell->setPort("\\B", gold_x); - or_gate_cell->setPort("\\Y", gate_masked); + or_gate_cell->setPort(ID::A, w_gate); + or_gate_cell->setPort(ID::B, gold_x); + or_gate_cell->setPort(ID::Y, gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w_gold->width; @@ -189,10 +189,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->setPort("\\A", gold_masked); - eq_cell->setPort("\\B", gate_masked); - eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort("\\Y"); + eq_cell->setPort(ID::A, gold_masked); + eq_cell->setPort(ID::B, gate_masked); + eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort(ID::Y); } else { @@ -202,10 +202,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->setPort("\\A", w_gold); - eq_cell->setPort("\\B", w_gate); - eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort("\\Y"); + eq_cell->setPort(ID::A, w_gold); + eq_cell->setPort(ID::B, w_gate); + eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort(ID::Y); } if (flag_make_outcmp) @@ -224,14 +224,14 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->setPort("\\A", all_conditions); - reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - all_conditions = reduce_cell->getPort("\\Y"); + reduce_cell->setPort(ID::A, all_conditions); + reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + all_conditions = reduce_cell->getPort(ID::Y); } if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->setPort("\\A", all_conditions); + assert_cell->setPort(ID::A, all_conditions); assert_cell->setPort("\\EN", State::S1); } @@ -243,8 +243,8 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->setPort("\\A", all_conditions); - not_cell->setPort("\\Y", w_trigger); + not_cell->setPort(ID::A, all_conditions); + not_cell->setPort(ID::Y, w_trigger); miter_module->fixup_ports(); @@ -315,7 +315,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL if (!cell->type.in("$assert", "$assume")) continue; - SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1); + SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1); SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1); if (cell->type == "$assert") { diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index b53bbfeb2..af8ffca9e 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena dict<SigBit, int> bit_user_cnt; for (auto wire : module->wires()) { - if (wire->name[0] == '\\' && wire->attributes.count("\\src")) + if (wire->name[0] == '\\' && wire->attributes.count(ID::src)) sigmap.add(wire); } @@ -489,12 +489,12 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena entry.port = conn.first; entry.portbit = i; - for (auto &s : cell->get_strpool_attribute("\\src")) + for (auto &s : cell->get_strpool_attribute(ID::src)) entry.src.insert(s); SigBit bit = sigmap(conn.second[i]); if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) { - for (auto &s : bit.wire->get_strpool_attribute("\\src")) + for (auto &s : bit.wire->get_strpool_attribute(ID::src)) entry.src.insert(s); entry.wire = bit.wire->name; entry.wirebit = bit.offset; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 436ac1b01..8ae572ad1 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -675,9 +675,9 @@ struct SatHelper strftime(stime, sizeof(stime), "%c", now); std::string module_fname = "unknown"; - auto apos = module->attributes.find("\\src"); + auto apos = module->attributes.find(ID::src); if(apos != module->attributes.end()) - module_fname = module->attributes["\\src"].decode_string(); + module_fname = module->attributes[ID::src].decode_string(); fprintf(f, "$date\n"); fprintf(f, " %s\n", stime); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index d5634b26d..c3e84ead5 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -303,19 +303,19 @@ struct SimInstance RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y; bool has_a, has_b, has_c, has_d, has_s, has_y; - has_a = cell->hasPort("\\A"); - has_b = cell->hasPort("\\B"); + has_a = cell->hasPort(ID::A); + has_b = cell->hasPort(ID::B); has_c = cell->hasPort("\\C"); has_d = cell->hasPort("\\D"); - has_s = cell->hasPort("\\S"); - has_y = cell->hasPort("\\Y"); + has_s = cell->hasPort(ID::S); + has_y = cell->hasPort(ID::Y); - if (has_a) sig_a = cell->getPort("\\A"); - if (has_b) sig_b = cell->getPort("\\B"); + if (has_a) sig_a = cell->getPort(ID::A); + if (has_b) sig_b = cell->getPort(ID::B); if (has_c) sig_c = cell->getPort("\\C"); if (has_d) sig_d = cell->getPort("\\D"); - if (has_s) sig_s = cell->getPort("\\S"); - if (has_y) sig_y = cell->getPort("\\Y"); + if (has_s) sig_s = cell->getPort(ID::S); + if (has_y) sig_y = cell->getPort(ID::Y); if (shared->debug) log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type)); @@ -505,10 +505,10 @@ struct SimInstance for (auto cell : formal_database) { string label = log_id(cell); - if (cell->attributes.count("\\src")) - label = cell->attributes.at("\\src").decode_string(); + if (cell->attributes.count(ID::src)) + label = cell->attributes.at(ID::src).decode_string(); - State a = get_state(cell->getPort("\\A"))[0]; + State a = get_state(cell->getPort(ID::A))[0]; State en = get_state(cell->getPort("\\EN"))[0]; if (cell->type == "$cover" && en == State::S1 && a != State::S1) diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index b9cd68883..7d759b9fd 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -118,6 +118,8 @@ struct ClkbufmapPass : public Pass { dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out; dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in; + IdString clkbuf_inhibit("\\clkbuf_inhibit"); + // Process submodules before module using them. std::vector<Module *> modules_sorted; pool<Module *> modules_processed; @@ -215,7 +217,7 @@ struct ClkbufmapPass : public Pass { if (wire->port_input && wire->port_output) continue; bool process_wire = module->selected(wire); - if (!select && wire->get_bool_attribute("\\clkbuf_inhibit")) + if (!select && wire->get_bool_attribute(clkbuf_inhibit)) process_wire = false; if (!process_wire) { // This wire is supposed to be bypassed, so make sure we don't buffer it in @@ -238,7 +240,7 @@ struct ClkbufmapPass : public Pass { buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); } else if (!sink_wire_bits.count(mapped_wire_bit)) { // Nothing to do. - } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) { + } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) { // Clock network not yet buffered, driven by one of // our cells or a top-level input -- buffer it. @@ -247,7 +249,7 @@ struct ClkbufmapPass : public Pass { Wire *iwire = module->addWire(NEW_ID); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); - if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) { + if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) { log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 2173049b4..5e26b0a18 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -41,16 +41,16 @@ struct InsbufPass : public Pass { { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); - std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y"; + IdString celltype = "$_BUF_", in_portname = ID::A, out_portname = ID::Y; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-buf" && argidx+3 < args.size()) { - celltype = args[++argidx]; - in_portname = args[++argidx]; - out_portname = args[++argidx]; + celltype = RTLIL::escape_id(args[++argidx]); + in_portname = RTLIL::escape_id(args[++argidx]); + out_portname = RTLIL::escape_id(args[++argidx]); continue; } break; @@ -76,9 +76,9 @@ struct InsbufPass : public Pass { continue; } - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->setPort(RTLIL::escape_id(in_portname), rhs); - cell->setPort(RTLIL::escape_id(out_portname), lhs); + Cell *cell = module->addCell(NEW_ID, celltype); + cell->setPort(in_portname, rhs); + cell->setPort(out_portname, lhs); log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs)); } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 88116eeec..ad169e70a 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -48,40 +48,40 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, int width = 1 + xorshift32(8); int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = width * swidth; wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); - wire = module->addWire("\\S"); + wire = module->addWire(ID::S); wire->width = swidth; wire->port_input = true; - cell->setPort("\\S", wire); + cell->setPort(ID::S, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } if (cell_type == "$fa") { int width = 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = width; wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); wire = module->addWire("\\C"); wire->width = width; @@ -93,10 +93,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, wire->port_output = true; cell->setPort("\\X", wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } if (cell_type == "$lcu") @@ -130,7 +130,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, int depth = 1 + xorshift32(6); int mulbits_a = 0, mulbits_b = 0; - RTLIL::Wire *wire_a = module->addWire("\\A"); + RTLIL::Wire *wire_a = module->addWire(ID::A); wire_a->width = 0; wire_a->port_input = true; @@ -158,15 +158,15 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, macc.ports.push_back(this_port); } - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1); wire->port_input = true; macc.bit_ports = wire; - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); macc.to_cell(cell); } @@ -175,14 +175,14 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, { int width = 1 + xorshift32(6); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < (1 << width); i++) @@ -196,14 +196,14 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, int width = 1 + xorshift32(8); int depth = 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < width*depth; i++) @@ -227,20 +227,20 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, } if (cell_type_flags.find('A') != std::string::npos) { - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); } if (cell_type_flags.find('B') != std::string::npos) { - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); if (cell_type_flags.find('h') != std::string::npos) wire->width = 1 + xorshift32(6); else wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); } if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { @@ -258,17 +258,17 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, } if (cell_type_flags.find('Y') != std::string::npos) { - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = 1 + xorshift32(8); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } if (muxdiv && cell_type.in("$div", "$mod")) { - auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B")); - auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y"))); - module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y")); - cell->setPort("\\Y", div_out); + auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); + auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); + module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); + cell->setPort(ID::Y, div_out); } if (cell_type == "$alu") @@ -282,12 +282,12 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort("\\BI", wire); wire = module->addWire("\\X"); - wire->width = GetSize(cell->getPort("\\Y")); + wire->width = GetSize(cell->getPort(ID::Y)); wire->port_output = true; cell->setPort("\\X", wire); wire = module->addWire("\\CO"); - wire->width = GetSize(cell->getPort("\\Y")); + wire->width = GetSize(cell->getPort(ID::Y)); wire->port_output = true; cell->setPort("\\CO", wire); } |