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-rw-r--r--passes/pmgen/.gitignore3
-rw-r--r--passes/pmgen/Makefile.inc9
-rw-r--r--passes/pmgen/ice40_dsp.cc125
-rw-r--r--passes/pmgen/ice40_dsp.pmg172
-rw-r--r--passes/pmgen/xilinx_dsp.cc149
-rw-r--r--passes/pmgen/xilinx_dsp.pmg102
-rw-r--r--passes/tests/test_autotb.cc5
7 files changed, 456 insertions, 109 deletions
diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore
index 0ad36ea2c..e52f3282f 100644
--- a/passes/pmgen/.gitignore
+++ b/passes/pmgen/.gitignore
@@ -1,2 +1 @@
-/ice40_dsp_pm.h
-/peepopt_pm.h
+/*_pm.h
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 7911132db..e33866670 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -1,14 +1,19 @@
OBJS += passes/pmgen/ice40_dsp.o
+OBJS += passes/pmgen/xilinx_dsp.o
OBJS += passes/pmgen/peepopt.o
# --------------------------------------
+passes/pmgen/%.o: passes/pmgen/%_pm.h
passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
+passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h
EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
+EXTRA_OBJS += passes/pmgen/xilinx_dsp_pm.h
.SECONDARY: passes/pmgen/ice40_dsp_pm.h
+.SECONDARY: passes/pmgen/xilinx_dsp_pm.h
-passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
- $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p ice40_dsp $(filter-out $<,$^)
+passes/pmgen/%_pm.h: passes/pmgen/pmgen.py passes/pmgen/%.pmg
+ $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p $* $(filter-out $<,$^)
# --------------------------------------
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 39d033a04..f6ae3a13f 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -23,6 +23,9 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
+template<class T> bool includes(const T &lhs, const T &rhs) {
+ return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
+}
#include "passes/pmgen/ice40_dsp_pm.h"
void create_ice40_dsp(ice40_dsp_pm &pm)
@@ -31,13 +34,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
#if 0
log("\n");
- log("ffA: %s\n", log_id(st.ffA, "--"));
- log("ffB: %s\n", log_id(st.ffB, "--"));
- log("mul: %s\n", log_id(st.mul, "--"));
- log("ffY: %s\n", log_id(st.ffY, "--"));
- log("addAB: %s\n", log_id(st.addAB, "--"));
- log("muxAB: %s\n", log_id(st.muxAB, "--"));
- log("ffS: %s\n", log_id(st.ffS, "--"));
+ log("ffA: %s\n", log_id(st.ffA, "--"));
+ log("ffB: %s\n", log_id(st.ffB, "--"));
+ log("mul: %s\n", log_id(st.mul, "--"));
+ log("ffH: %s\n", log_id(st.ffH, "--"));
+ log("addAB: %s\n", log_id(st.addAB, "--"));
+ log("muxAB: %s\n", log_id(st.muxAB, "--"));
+ log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
+ log("ffO_hi: %s\n", log_id(st.ffO_hi, "--"));
#endif
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -52,47 +56,38 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
return;
}
- if (GetSize(st.sigS) > 32) {
- log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS));
+ if (GetSize(st.sigO) > 33) {
+ log(" adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
return;
}
- if (GetSize(st.sigY) > 32) {
- log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY));
+ if (GetSize(st.sigH) > 32) {
+ log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
return;
}
- bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool();
-
- if (mul_signed) {
- log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n");
- return;
- }
-
- log(" replacing $mul with SB_MAC16 cell.\n");
+ log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
pm.module->swap_names(cell, st.mul);
// SB_MAC16 Input Interface
-
SigSpec A = st.sigA;
- A.extend_u0(16, mul_signed);
+ log_assert(GetSize(A) == 16);
SigSpec B = st.sigB;
- B.extend_u0(16, mul_signed);
+ log_assert(GetSize(B) == 16);
- SigSpec CD;
- if (st.muxA)
- CD = st.muxA->getPort("\\B");
- if (st.muxB)
- CD = st.muxB->getPort("\\A");
- CD.extend_u0(32, mul_signed);
+ SigSpec CD = st.sigCD;
+ if (CD.empty())
+ CD = RTLIL::Const(0, 32);
+ else
+ log_assert(GetSize(CD) == 32);
cell->setPort("\\A", A);
cell->setPort("\\B", B);
- cell->setPort("\\C", CD.extract(0, 16));
- cell->setPort("\\D", CD.extract(16, 16));
+ cell->setPort("\\C", CD.extract(16, 16));
+ cell->setPort("\\D", CD.extract(0, 16));
cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
@@ -105,7 +100,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\IRSTTOP", State::S0);
cell->setPort("\\IRSTBOT", State::S0);
- if (st.clock_vld)
+ if (st.clock != SigBit())
{
cell->setPort("\\CLK", st.clock);
cell->setPort("\\CE", State::S1);
@@ -119,11 +114,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
- if (st.ffY)
- log(" ffY:%s", log_id(st.ffY));
+ if (st.ffH)
+ log(" ffH:%s", log_id(st.ffH));
- if (st.ffS)
- log(" ffS:%s", log_id(st.ffS));
+ if (st.ffO_lo)
+ log(" ffO_lo:%s", log_id(st.ffO_lo));
+ if (st.ffO_hi)
+ log(" ffO_hi:%s", log_id(st.ffO_hi));
log("\n");
}
@@ -140,21 +137,43 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
cell->setPort("\\CI", State::Sx);
- cell->setPort("\\CO", pm.module->addWire(NEW_ID));
cell->setPort("\\ACCUMCI", State::Sx);
cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
// SB_MAC16 Output Interface
- SigSpec O = st.ffS ? st.sigS : st.sigY;
+ SigSpec O = st.sigO;
+ int O_width = GetSize(O);
+ if (O_width == 33) {
+ log_assert(st.addAB);
+ // If we have a signed multiply-add, then perform sign extension
+ // TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
+ if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
+ pm.module->connect(O[-1], O[-2]);
+ else
+ cell->setPort("\\CO", O[-1]);
+ O.remove(O_width-1);
+ }
+ else
+ cell->setPort("\\CO", pm.module->addWire(NEW_ID));
+ log_assert(GetSize(O) <= 32);
if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
cell->setPort("\\O", O);
+ bool accum = false;
if (st.addAB) {
- log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+ if (st.addA)
+ accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
+ else if (st.addB)
+ accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
+ else log_abort();
+ if (accum)
+ log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+ else
+ log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
} else {
@@ -182,28 +201,36 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\C_REG", State::S0);
cell->setParam("\\D_REG", State::S0);
- cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
- cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
- cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
+ cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+ cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+ cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
- cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+ cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
- cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
+ cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
- cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+ cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO_lo ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
- cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
+ cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
cell->setParam("\\MODE_8x8", State::S0);
- cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0);
- cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0);
+ cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
+ cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
pm.autoremove(st.mul);
- pm.autoremove(st.ffY);
- pm.autoremove(st.ffS);
+ pm.autoremove(st.ffH);
+ pm.autoremove(st.addAB);
+ if (st.ffO_lo) {
+ SigSpec O = st.sigO.extract(0,16);
+ st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+ }
+ if (st.ffO_hi) {
+ SigSpec O = st.sigO.extract(16,16);
+ st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+ }
}
struct Ice40DspPass : public Pass {
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 1f3590d4e..f1f533187 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,87 +1,101 @@
pattern ice40_dsp
state <SigBit> clock
-state <bool> clock_pol clock_vld
-state <SigSpec> sigA sigB sigY sigS
+state <bool> clock_pol
+state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> addAB muxAB
match mul
- select mul->type.in($mul)
+ select mul->type.in($mul, $__MUL16X16)
select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
select GetSize(mul->getPort(\Y)) > 10
endmatch
match ffA
+ // TODO: Support $dffe too by checking if all enable signals are identical
select ffA->type.in($dff)
- // select nusers(port(ffA, \Q)) == 2
- index <SigSpec> port(ffA, \Q) === port(mul, \A)
+ filter !port(mul, \A).remove_const().empty()
+ filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
optional
endmatch
-code sigA clock clock_pol clock_vld
+code sigA clock clock_pol
sigA = port(mul, \A);
if (ffA) {
- sigA = port(ffA, \D);
+ for (auto b : port(ffA, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
clock = port(ffA, \CLK).as_bit();
clock_pol = param(ffA, \CLK_POLARITY).as_bool();
- clock_vld = true;
+
+ sigA.replace(port(ffA, \Q), port(ffA, \D));
}
endcode
match ffB
select ffB->type.in($dff)
- // select nusers(port(ffB, \Q)) == 2
- index <SigSpec> port(ffB, \Q) === port(mul, \B)
+ filter !port(mul, \B).remove_const().empty()
+ filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
optional
endmatch
-code sigB clock clock_pol clock_vld
+code sigB clock clock_pol
sigB = port(mul, \B);
if (ffB) {
- sigB = port(ffB, \D);
+ for (auto b : port(ffB, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
SigBit c = port(ffB, \CLK).as_bit();
bool cp = param(ffB, \CLK_POLARITY).as_bool();
- if (clock_vld && (c != clock || cp != clock_pol))
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
- clock_vld = true;
+
+ sigB.replace(port(ffB, \Q), port(ffB, \D));
}
endcode
-match ffY
- select ffY->type.in($dff)
- select nusers(port(ffY, \D)) == 2
- index <SigSpec> port(ffY, \D) === port(mul, \Y)
+match ffH
+ select ffH->type.in($dff)
+ select nusers(port(ffH, \D)) == 2
+ index <SigSpec> port(ffH, \D) === port(mul, \Y)
optional
endmatch
-code sigY clock clock_pol clock_vld
- sigY = port(mul, \Y);
+code sigH sigO clock clock_pol
+ sigH = port(mul, \Y);
+ sigO = sigH;
+
+ if (ffH) {
+ sigH = port(ffH, \Q);
+ for (auto b : sigH)
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
- if (ffY) {
- sigY = port(ffY, \Q);
- SigBit c = port(ffY, \CLK).as_bit();
- bool cp = param(ffY, \CLK_POLARITY).as_bool();
+ sigO = sigH;
- if (clock_vld && (c != clock || cp != clock_pol))
+ SigBit c = port(ffH, \CLK).as_bit();
+ bool cp = param(ffH, \CLK_POLARITY).as_bool();
+
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
- clock_vld = true;
}
endcode
match addA
select addA->type.in($add)
select nusers(port(addA, \A)) == 2
- index <SigSpec> port(addA, \A) === sigY
+ index <SigSpec> port(addA, \A) === sigH
optional
endmatch
@@ -89,74 +103,120 @@ match addB
if !addA
select addB->type.in($add, $sub)
select nusers(port(addB, \B)) == 2
- index <SigSpec> port(addB, \B) === sigY
+ index <SigSpec> port(addB, \B) === sigH
optional
endmatch
-code addAB sigS
+code addAB sigCD sigO
if (addA) {
addAB = addA;
- sigS = port(addA, \B);
+ sigCD = port(addAB, \B);
+ sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
}
if (addB) {
addAB = addB;
- sigS = port(addB, \A);
+ sigCD = port(addAB, \A);
+ sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
}
if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB);
- int actual_mul_width = GetSize(sigY);
- int actual_acc_width = GetSize(sigS);
+ int actual_mul_width = GetSize(sigH);
+ int actual_acc_width = GetSize(sigO);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
- if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+ if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool()))
reject;
+
+ sigO = port(addAB, \Y);
}
endcode
match muxA
- if addAB
select muxA->type.in($mux)
select nusers(port(muxA, \A)) == 2
- index <SigSpec> port(muxA, \A) === port(addAB, \Y)
+ index <SigSpec> port(muxA, \A) === sigO
optional
endmatch
match muxB
- if addAB
if !muxA
select muxB->type.in($mux)
select nusers(port(muxB, \B)) == 2
- index <SigSpec> port(muxB, \B) === port(addAB, \Y)
+ index <SigSpec> port(muxB, \B) === sigO
optional
endmatch
code muxAB
- muxAB = addAB;
if (muxA)
muxAB = muxA;
- if (muxB)
+ else if (muxB)
muxAB = muxB;
endcode
-match ffS
- if muxAB
- select ffS->type.in($dff)
- select nusers(port(ffS, \D)) == 2
- index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
- index <SigSpec> port(ffS, \Q) === sigS
+match ffO_lo
+ select ffO_lo->type.in($dff)
+ filter nusers(sigO.extract(0,16)) == 2
+ filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
+ optional
endmatch
-code clock clock_pol clock_vld
- if (ffS) {
- SigBit c = port(ffS, \CLK).as_bit();
- bool cp = param(ffS, \CLK_POLARITY).as_bool();
-
- if (clock_vld && (c != clock || cp != clock_pol))
- reject;
+match ffO_hi
+ select ffO_hi->type.in($dff)
+ filter nusers(sigO.extract(16,16)) == 2
+ filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
+ optional
+endmatch
- clock = c;
- clock_pol = cp;
- clock_vld = true;
+code clock clock_pol sigO sigCD
+ if (ffO_lo || ffO_hi) {
+ if (ffO_lo) {
+ for (auto b : port(ffO_lo, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffO_lo, \CLK).as_bit();
+ bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
+
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
+ reject;
+
+ clock = c;
+ clock_pol = cp;
+
+ if (port(ffO_lo, \Q) != sigO.extract(0,16))
+ sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
+ }
+
+ if (ffO_hi) {
+ for (auto b : port(ffO_hi, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffO_hi, \CLK).as_bit();
+ bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
+
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
+ reject;
+
+ clock = c;
+ clock_pol = cp;
+
+ if (port(ffO_hi, \Q) != sigO.extract(16,16))
+ sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
+ }
+
+ // Loading value into output register is not
+ // supported unless using accumulator
+ if (muxAB) {
+ if (sigCD != sigO)
+ reject;
+ if (muxA)
+ sigCD = port(muxAB, \B);
+ else if (muxB)
+ sigCD = port(muxAB, \A);
+ else log_abort();
+ sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
+ }
}
endcode
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
new file mode 100644
index 000000000..be510b4cb
--- /dev/null
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -0,0 +1,149 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+template<class T> bool includes(const T &lhs, const T &rhs) {
+ return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
+}
+#include "passes/pmgen/xilinx_dsp_pm.h"
+
+void pack_xilinx_dsp(xilinx_dsp_pm &pm)
+{
+ auto &st = pm.st_xilinx_dsp;
+
+#if 1
+ log("\n");
+ log("ffA: %s\n", log_id(st.ffA, "--"));
+ log("ffB: %s\n", log_id(st.ffB, "--"));
+ log("dsp: %s\n", log_id(st.dsp, "--"));
+ log("ffP: %s\n", log_id(st.ffP, "--"));
+ log("muxP: %s\n", log_id(st.muxP, "--"));
+ log("sigPused: %s\n", log_signal(st.sigPused));
+ log_module(pm.module);
+#endif
+
+ log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.dsp));
+
+ Cell *cell = st.dsp;
+ log_assert(cell);
+
+ if (st.clock != SigBit())
+ {
+ cell->setPort("\\CLK", st.clock);
+
+ if (st.ffA) {
+ SigSpec A = cell->getPort("\\A");
+ SigSpec D = st.ffA->getPort("\\D");
+ SigSpec Q = st.ffA->getPort("\\Q");
+ A.replace(Q, D);
+ cell->setPort("\\A", A);
+ cell->setParam("\\AREG", State::S1);
+ if (st.ffA->type == "$dff")
+ cell->setPort("\\CEA2", State::S1);
+ else if (st.ffA->type == "$dffe")
+ cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
+ else log_abort();
+ }
+ if (st.ffB) {
+ SigSpec B = cell->getPort("\\B");
+ SigSpec D = st.ffB->getPort("\\D");
+ SigSpec Q = st.ffB->getPort("\\Q");
+ B.replace(Q, D);
+ cell->setPort("\\B", B);
+ cell->setParam("\\BREG", State::S1);
+ if (st.ffB->type == "$dff")
+ cell->setPort("\\CEB2", State::S1);
+ else if (st.ffB->type == "$dffe")
+ cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
+ else log_abort();
+ }
+ if (st.ffP) {
+ SigSpec P = cell->getPort("\\P");
+ SigSpec D;
+ if (st.muxP)
+ D = st.muxP->getPort("\\B");
+ else
+ D = st.ffP->getPort("\\D");
+ SigSpec Q = st.ffP->getPort("\\Q");
+ P.replace(pm.sigmap(D), Q);
+ cell->setPort("\\P", P);
+ cell->setParam("\\PREG", State::S1);
+ if (st.ffP->type == "$dff")
+ cell->setPort("\\CEP", State::S1);
+ else if (st.ffP->type == "$dffe")
+ cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
+ else log_abort();
+
+ st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+ }
+
+ log(" clock: %s (%s)", log_signal(st.clock), "posedge");
+
+ if (st.ffA)
+ log(" ffA:%s", log_id(st.ffA));
+
+ if (st.ffB)
+ log(" ffB:%s", log_id(st.ffB));
+
+ if (st.ffP)
+ log(" ffY:%s", log_id(st.ffP));
+
+ log("\n");
+ }
+
+ pm.blacklist(cell);
+}
+
+struct Ice40DspPass : public Pass {
+ Ice40DspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" xilinx_dsp [options] [selection]\n");
+ log("\n");
+ log("Pack registers into Xilinx DSPs\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing XILINX_DSP pass (pack DSPs).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp);
+ }
+} Ice40DspPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
new file mode 100644
index 000000000..a97ab4dd5
--- /dev/null
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -0,0 +1,102 @@
+pattern xilinx_dsp
+
+state <SigBit> clock
+state <SigSpec> sigPused
+
+match dsp
+ select dsp->type.in(\DSP48E1)
+endmatch
+
+match ffA
+ select ffA->type.in($dff, $dffe)
+ // DSP48E1 does not support clock inversion
+ select param(ffA, \CLK_POLARITY).as_bool()
+ filter !port(dsp, \A).remove_const().empty()
+ filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
+ optional
+endmatch
+
+code clock
+ if (ffA)
+ clock = port(ffA, \CLK).as_bit();
+endcode
+
+match ffB
+ select ffB->type.in($dff, $dffe)
+ // DSP48E1 does not support clock inversion
+ select param(ffB, \CLK_POLARITY).as_bool()
+ filter !port(dsp, \B).remove_const().empty()
+ filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
+ optional
+endmatch
+
+code clock
+ if (ffB) {
+ SigBit c = port(ffB, \CLK).as_bit();
+
+ if (clock != SigBit() && c != clock)
+ reject;
+
+ clock = c;
+ }
+endcode
+
+// Extract the bits of P that actually have a consumer
+// (as opposed to being a sign extension)
+code sigPused
+ SigSpec P = port(dsp, \P);
+ int i;
+ for (i = GetSize(P); i > 0; i--)
+ if (nusers(P[i-1]) > 1)
+ break;
+ sigPused = P.extract(0, i).remove_const();
+endcode
+
+match ffP
+ if !sigPused.empty()
+ select ffP->type.in($dff, $dffe)
+ select nusers(port(ffP, \D)) == 2
+ // DSP48E1 does not support clock inversion
+ select param(ffP, \CLK_POLARITY).as_bool()
+ filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
+ filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
+ optional
+endmatch
+
+// $mux cell left behind by dff2dffe
+// would prefer not to run 'opt_expr -mux_undef'
+// since that would lose information helpful for
+// efficient wide-mux inference
+match muxP
+ if !sigPused.empty() && !ffP
+ select muxP->type.in($mux)
+ select nusers(port(muxP, \B)) == 2
+ select port(muxP, \A).is_fully_undef()
+ filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
+ filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
+ optional
+endmatch
+
+match ffY
+ if muxP
+ select ffY->type.in($dff, $dffe)
+ select nusers(port(ffY, \D)) == 2
+ // DSP48E1 does not support clock inversion
+ select param(ffY, \CLK_POLARITY).as_bool()
+ filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
+ filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
+endmatch
+
+code ffP clock
+ if (ffY)
+ ffP = ffY;
+
+ if (ffP) {
+ SigBit c = port(ffP, \CLK).as_bit();
+
+ if (clock != SigBit() && c != clock)
+ reject;
+
+ clock = c;
+ }
+endcode
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index bfb1d6642..7f11e54f3 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -348,6 +348,11 @@ struct TestAutotbBackend : public Backend {
log(" -n <int>\n");
log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
+ log(" -seed <int>\n");
+ log(" seed used for pseudo-random number generation (default = 0).\n");
+ log(" a value of 0 will cause an arbitrary seed to be chosen, based on\n");
+ log(" the current system time.\n");
+ log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-11 08:34:24 +0000