diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/add.cc | 37 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 14 | ||||
| -rw-r--r-- | passes/techmap/deminout.cc | 3 |
3 files changed, 25 insertions, 29 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index dd05ac81f..62c253bed 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -24,24 +24,23 @@ PRIVATE_NAMESPACE_BEGIN static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) { - RTLIL::Wire *wire = NULL; + RTLIL::Wire *wire = nullptr; name = RTLIL::escape_id(name); if (module->count_id(name) != 0) { - if (module->wires_.count(name) > 0) - wire = module->wires_.at(name); + wire = module->wire(name); - if (wire != NULL && wire->width != width) - wire = NULL; + if (wire != nullptr && wire->width != width) + wire = nullptr; - if (wire != NULL && wire->port_input != flag_input) - wire = NULL; + if (wire != nullptr && wire->port_input != flag_input) + wire = nullptr; - if (wire != NULL && wire->port_output != flag_output) - wire = NULL; + if (wire != nullptr && wire->port_output != flag_output) + wire = nullptr; - if (wire == NULL) + if (wire == nullptr) log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); log("Module %s already has such an object.\n", module->name.c_str()); @@ -53,7 +52,6 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire->port_output = flag_output; if (flag_input || flag_output) { - wire->port_id = module->wires_.size(); module->fixup_ports(); } @@ -63,21 +61,20 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (!flag_global) return; - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - if (design->modules_.count(it.second->type) == 0) + RTLIL::Module *mod = design->module(cell->type); + if (mod == nullptr) continue; - - RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_blackbox_attribute()) continue; - if (it.second->hasPort(name)) + if (cell->hasPort(name)) continue; - it.second->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); + cell->setPort(name, wire); + log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str()); } } @@ -155,9 +152,9 @@ struct AddPass : public Pass { extra_args(args, argidx, design); - for (auto &mod : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = mod.second; + log_assert(module != nullptr); if (!design->selected_whole_module(module->name)) continue; if (module->get_bool_attribute("\\blackbox")) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 5e650230d..212e0692d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -332,9 +332,9 @@ struct Abc9Pass : public ScriptPass tempdir_name = make_temp_dir(tempdir_name); if (!lut_mode) - run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str())); - run(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str())); - run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); + run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str())); + run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str())); + run_nocheck(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); @@ -350,9 +350,9 @@ struct Abc9Pass : public ScriptPass if (!lut_mode) abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str()); abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str()); - run(abc9_exe_cmd); - run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str())); - run("abc9_ops -reintegrate"); + run_nocheck(abc9_exe_cmd); + run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str())); + run_nocheck("abc9_ops -reintegrate"); } else log("Don't call ABC as there is nothing to map.\n"); @@ -361,7 +361,7 @@ struct Abc9Pass : public ScriptPass log("Removing temp directory.\n"); remove_directory(tempdir_name); } - + mod->check(); active_design->selection().selected_modules.clear(); log_pop(); } diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index b976b401b..35d43b106 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -121,8 +121,7 @@ struct DeminoutPass : public Pass { goto tribuf_bit; } else { tribuf_bit: - if (bits_used.count(bit)) - new_input = true; + new_input = true; } } |