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-rw-r--r--passes/opt/wreduce.cc29
-rw-r--r--passes/pmgen/Makefile.inc2
-rw-r--r--passes/pmgen/pmgen.py17
3 files changed, 34 insertions, 14 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 09983bc67..1f7222e49 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -53,6 +53,7 @@ struct WreduceWorker
std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
std::set<SigBit> work_queue_bits;
pool<SigBit> keep_bits;
+ dict<SigBit, State> init_bits;
WreduceWorker(WreduceConfig *config, Module *module) :
config(config), module(module), mi(module) { }
@@ -141,6 +142,7 @@ struct WreduceWorker
SigSpec sig_d = mi.sigmap(cell->getPort("\\D"));
SigSpec sig_q = mi.sigmap(cell->getPort("\\Q"));
+ Const initval;
int width_before = GetSize(sig_q);
@@ -150,16 +152,24 @@ struct WreduceWorker
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
bool sign_ext = !zero_ext;
+ for (int i = 0; i < GetSize(sig_q); i++) {
+ SigBit bit = sig_q[i];
+ if (init_bits.count(bit))
+ initval.bits.push_back(init_bits.at(bit));
+ else
+ initval.bits.push_back(State::Sx);
+ }
+
for (int i = GetSize(sig_q)-1; i >= 0; i--)
{
- if (zero_ext && sig_d[i] == State::S0) {
+ if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
module->connect(sig_q[i], State::S0);
sig_d.remove(i);
sig_q.remove(i);
continue;
}
- if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1]) {
+ if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
module->connect(sig_q[i], sig_q[i-1]);
sig_d.remove(i);
sig_q.remove(i);
@@ -167,7 +177,7 @@ struct WreduceWorker
}
auto info = mi.query(sig_q[i]);
- if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
+ if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
sig_d.remove(i);
sig_q.remove(i);
zero_ext = false;
@@ -183,10 +193,11 @@ struct WreduceWorker
if (GetSize(sig_q) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
+ module->remove(cell);
return;
}
- log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
+ log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
log_id(module), log_id(cell), log_id(cell->type));
for (auto bit : sig_d)
@@ -376,10 +387,18 @@ struct WreduceWorker
void run()
{
- for (auto w : module->wires())
+ for (auto w : module->wires()) {
if (w->get_bool_attribute("\\keep"))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
+ if (w->attributes.count("\\init")) {
+ Const initval = w->attributes.at("\\init");
+ SigSpec initsig = mi.sigmap(w);
+ int width = std::min(GetSize(initval), GetSize(initsig));
+ for (int i = 0; i < width; i++)
+ init_bits[initsig[i]] = initval[i];
+ }
+ }
for (auto c : module->selected_cells())
work_queue_cells.insert(c);
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index b9682612b..e0dd0fc06 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -5,4 +5,4 @@ EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
.SECONDARY: passes/pmgen/ice40_dsp_pm.h
passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
- $(P) mkdir -p passes/pmgen && cd passes/pmgen && python3 $^
+ $(P) mkdir -p passes/pmgen && python3 $^
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 166d3963a..762d8621f 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -7,8 +7,9 @@ import pprint
pp = pprint.PrettyPrinter(indent=4)
pmgfile = sys.argv[1]
-prefix = pmgfile.split("/")[-1]
-prefix = prefix.split(".")[0]
+assert pmgfile.endswith(".pmg")
+prefix = pmgfile[0:-4]
+pmname = prefix.split('/')[-1]
state_types = dict()
udata_types = dict()
@@ -84,7 +85,7 @@ with open(pmgfile, "r") as f:
cmd = line.split()
if len(cmd) == 0 or cmd[0].startswith("//"): continue
cmd = cmd[0]
-
+
if cmd == "state":
m = re.match(r"^state\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line)
assert m
@@ -189,10 +190,10 @@ with open("%s_pm.h" % prefix, "w") as f:
print("YOSYS_NAMESPACE_BEGIN", file=f)
print("", file=f)
- print("struct {}_pm {{".format(prefix), file=f)
+ print("struct {}_pm {{".format(pmname), file=f)
print(" Module *module;", file=f)
print(" SigMap sigmap;", file=f)
- print(" std::function<void()> on_accept;".format(prefix), file=f)
+ print(" std::function<void()> on_accept;".format(pmname), file=f)
print("", file=f)
for index in range(len(blocks)):
@@ -290,7 +291,7 @@ with open("%s_pm.h" % prefix, "w") as f:
print(" }", file=f)
print("", file=f)
- print(" {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
+ print(" {}_pm(Module *module, const vector<Cell*> &cells) :".format(pmname), file=f)
print(" module(module), sigmap(module) {", file=f)
for s, t in sorted(udata_types.items()):
if t.endswith("*"):
@@ -320,7 +321,7 @@ with open("%s_pm.h" % prefix, "w") as f:
print(" }", file=f)
print("", file=f)
- print(" ~{}_pm() {{".format(prefix), file=f)
+ print(" ~{}_pm() {{".format(pmname), file=f)
print(" for (auto cell : autoremove_cells)", file=f)
print(" module->remove(cell);", file=f)
print(" }", file=f)
@@ -339,7 +340,7 @@ with open("%s_pm.h" % prefix, "w") as f:
print(" }", file=f)
print("", file=f)
- print(" void run(std::function<void({}_pm&)> on_accept_f) {{".format(prefix), file=f)
+ print(" void run(std::function<void({}_pm&)> on_accept_f) {{".format(pmname), file=f)
print(" run([&](){on_accept_f(*this);});", file=f)
print(" }", file=f)
print("", file=f)
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-04 16:16:48 +0000